PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 168

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

13.1
13
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
Functional Timing
Receive Interface Timing
Figure 35 below, shows the relative timing of the receive interface. The LVDS links carry
SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries, justification
events and alarm conditions are encoded in special control characters. The upstream devices
sourcing the links share a common clock and have a common transport frame alignment that is
synchronized by the Receive Serial Interface Frame Pulse signal (RC1FP). Due to phase noise of
clock multiplication circuits and backplane routing or cable length discrepancies, the links will
not phase aligned to each other but are frequency locked. The delay from RC1FP being sampled
high to the first and last C1 character is shown in Figure 35 In this example, the first C1 is
delivered on link RN[X]/RP[X]. The delay to the last C1 represents the time when the all the
links have delivered their C1 character. In the example below, link RN[Y]/RP[Y] is shown to be
the slowest. The minimum value for the internal programmable delay (RC1DLY[13:0]) is the
delay through the SBS
Consequently, the external system must ensure that the relative delays between all the receive
LVDS links be less than 16 bytes. The relative phases of the links in Figure 35 are shown for
illustrative purposes only. Links may have different delays relative to other links than what is
shown.
Figure 36 Receive Interface Timing
2
depending on the mode employed.
SYSCLK
RC1FP
RP[X]/
RN[X]
RN[Y]/
RP[Y]
This delay will be either one frame (9720 clock cycles) or one row (1080 clock cycles)
2
plus 15. The maximum value is the delay through the SBS plus 31.
...
...
...
RC1DLY[13:0] Delay
S4,3/
A2
S1,1/
C1
S2,1/
Z0
Max Delay between
First and Last J0s
...
...
...
NSE-8G™ Standard Product Data Sheet
Max Delay until internal Frame Pulse
S4,3/
A2
S1,1/
C1
S2,1/
Z0
Min Delay until internal
Frame Pulse
Preliminary
...
...
...
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