PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 150

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

12.11 ILC Operation
12.12 ILC CPU Operations
12.12.1 Accessing the Transmit Message FIFO
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
Note: It is vital to ensure that switching of the DS0 bytes containing CAS bits be performed
correctly through software configuration. That is, these bytes should all be preserved and
switched to the same output link to preserve the CAS for downstream devices.
Operating each of the 32 ILC blocks requires the same procedure. Each ILC will be operating
independently and wait states required for each ILC can be satisfied by interleaving the access
cycles of several ILC blocks together.
The ILC is synchronized by the C1 pulse accompanying the input data stream on the
TelecomBus. It preloads a 9720 counter using this C1 pulse. C1 as shown in Figure 26, will be
high when the byte in column 25, row 1 is on the input data pins. A 2 bit counter is also kept to
keep track of the 4-frame multiframe, ie. 4 x 9720 count. This is indicated by C1 being present
only in the first frame of a multiframe. (could be 1in 4 or higher multiples).
Figure 26 C1 Position in the First Row
The ILC inserts and retrieves messages from the transport overhead of the SONET/SDH frame on
the telecom-bus. Figure 27 illustrates the four rows carrying the four messages per frame.
The messages are inserted on an availability basis into the four message rows shown in Figure 27,
rows 3,6,7 and 8. The header is always placed into columns 1 and 2. The Message itself is always
placed MSByte first into columns 3 – 34, in FIFO order. The CRC-16, calculated over the header
and message, is placed into columns 35 and 36.
If no message is available, internal hardware will automatically insert zeros into the message
bytes. Even if no message is available (32 of 36 bytes), the header(2 of 36 bytes) can still be
carrying valid bits for the far end, as such even if the message is invalid, the Header and CRC are
still generated and inserted. The header’s Valid bit is not set as an indication to the far end to
discard the message (not insert the null message into its RxFIFO).
Access registers in the following order:
Column
Row 1
CMP inputs will be sampled every 48th frame at the internally flywheeled RC1FP
location.
If enabled, FRAMEI will occur every 48 frame at the internally flywheeled RC1FP
location.
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2
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NSE-8G™ Standard Product Data Sheet
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Preliminary
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C1