PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 147

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

12.6.3
12.6.4
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
Go to step 1 to begin the mapping change for a new byte in the frame.
It is possible to read configurations from the offline connection memory page. The following
example shows this reading operation.
Example: Suppose one wishes to read which DIN ports map to DOUT[17:12][12:0] for the
4097th byte of the frame within the offline connection memory page.
Steps:
1. CPU writes 0x80081000 to the DCB Access Mode register. (A binary value of 010XX on
2. Wait for six SYSCLK cycles.
3. CPU reads the mapping from the DCB Configuration Output register.
Note:
1.
2.
3.
There are two ways in which a connection memory page copy can occur; forced and automatic.
In forced mode, the CPU initiates a page copy by writing to the DCB Interrupt Status register.
The page copy begins immediately after being initiated.
In automatic mode, the AUTO field must be set to logic one. When a connection memory page
swap occurs, the online connection memory page is copied to the offline connection memory
page.
Interrupt generation to signal the page copying status can be enabled to simplify software
scheduling by setting the UPDATEE field in the DCB Configuration register to logic one. In this
mode, the UPDATEI field in the DCB Interrupt Status register can be used as the interrupt signal
to control the microprocessor.
Alternatively, the microprocessor can poll the UPDATEV field within the DCB Configuration
register to detect the status of the connection memory page update logic. Logic one indicates
copying in progress and logic zero indicates copying complete.
Reading Configurations
DCB Online to Offline Memory Page Copy
PORTADDR[4:0] indicates to supply the mapping the Configuration Port 17-12 register.)
The Access Mode register should NOT be accessed more frequently than once ever 4 SYSCLK cycles
when initiating write transfers.
When initiating a read from the offline connection memory page to the Configuration Output register,
there is a latency of 6 SYSCLK cycles from when a read is initiated till when valid data appears on
CFG_O.
User should perform this operation only when there is no page swap pending (SWAPV = ‘0’) and page
copy is inactive (UPDATEV = ‘0’).
Triggers a write to offline connection memory page at 0x1000.
NSE-8G™ Standard Product Data Sheet
Preliminary
146