CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 87

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

10.6.1 Serial Peripheral Control Register
MC68HC05C4A
MOTOROLA
—
Rev. 4.0
Address:
SPIE — Serial Peripheral Interrupt Enable
SPE — Serial Peripheral System Enable
MSTR — Master Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
Reset:
Read:
Write:
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
0 = SPI system off
1 = SPI system on
0 = Slave mode
1 = Master mode
$000A
SPID
Bit 7
0
Serial Peripheral Interface (SPI)
Figure 10-4. SPI Control Register (SPCR)
Figure
= Unimplemented
SPD
6
0
10-1.
5
0
MSTR
U = Unaffected
4
0
CPOL
3
0
Serial Peripheral Interface (SPI)
General Release Specification
CPHA
2
0
SPR1
U
1
SPI Registers
SPR0
Bit 0
0
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