CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 59

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CM68HC05C4ACFB

Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
MC68HC05C4A
MOTOROLA
Rev. 4.0
ICIE — Input Capture Interrupt Enable
OCIE — Output Compare Interrupt Enable
TOIE — Timer Overflow Interrupt Enable
IEDG — Input Edge
OLVL — Output Level
Bits 2, 3, and 4 — Not used
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
Reset does not affect the IEDG bit.
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
Always read 0
1 = Interrupt enabled
0 = Interrupt disabled
1 = Interrupt enabled
0 = Interrupt disabled
1 = Interrupt enabled
0 = Interrupt disabled
1 = Positive edge
0 = Negative edge
1 = High output
0 = Low output
Timer
General Release Specification
Timer Control Register
Timer
59

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