CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 78

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

Serial Communications Interface (SCI)
9.6.5 Baud Rate Register
General Release Specification
78
Address:
NF — Receiver Noise Flag
FE — Receiver Framing Error
The baud rate register selects the baud rate for both the receiver and the
transmitter.
SCP1 and SCP0 — SCI Prescaler Select Bits
Reset:
Read:
Write:
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR, and then reading the SCDR. Reset clears
the FE bit.
These read/write bits control prescaling of the baud rate generator
clock, as shown in
1 = Noise detected in SCDR
0 = No noise detected in SCDR
1 = Framing error
0 = No framing error
U = Unaffected
Serial Communications Interface (SCI)
$000D
Bit 7
0
0
Figure 9-8. Baud Rate Register (BAUD)
6
0
0
Table
SCP1
5
0
9-1. Resets clear both SCP1 and SCP0.
SCP0
4
0
3
0
0
MC68HC05C4A
SCR2
U
2
SCR1
U
1
MOTOROLA
—
Rev. 4.0
SCR0
Bit 0
U