11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 39

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

The goal is to choose the highest crystal frequency from
Table 10 that generates the smallest value of N
The equation establishing the output frequency (f
function of the input VCXO frequency is
where N
Choose a few different crystal frequencies from Table 10
and factor both the input VCXO and output clock fre-
quencies into prime numbers. Look for the factors that
will give the smallest modulus for N
F
duced factors from Eqn. 1 are in Table 25.
Table 25: Clock Regenerator Example
A 19.44MHz crystal provides the smallest modulus for N
(N
Finally, choose a Post Divider (N
the VCO frequency in its most comfortable range. The
VCO frequency (f
Selecting an overall modulus of N
quency at 155.52MHz when the loop is locked.
VCXO
VCXO FREQUENCY
R
=3) with the highest crystal frequency.
FROM Table 10
(f
. The output and VCXO frequencies and the re-
VCXO
25.248
24.576
20.00
19.44
F
, MHz)
is the Feedback Divider modulus.
VCO
f
f
VCXO
CLK
) can be calculated by
f
VCO
19440000
51840000
20000000
51840000
51840000
25248000
51840000
24576000
N
N
F
f
R
f
VCXO
f
CLK
CLK
(Eqn. 1)
N
Px
Px
Px
) modulus that keeps
=3 sets the VCO fre-
R
with the largest
125
324
540
135
263
R.
N
N
64
8
3
CLK
F
R
) as a
R
39
15.2
To generate a de-jittered output frequency of 51.84MHz
from an 8kHz reference, program the following (refer to
Figure 33):
These settings provide the highest frequency at the Main
Loop Phase Frequency Detector of 6.48MHz. The use of
a 19.44MHz crystal requires that XLROM[2:0] be set to
three as shown in Table 10.
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Program the VCXO Control ROM to 3 via
XLROM[2:0] to select an external 19.44MHz crystal
Enable the VCXO fine tune via XLVTEN=1
Enable the Crystal Loop PFD via XLPDEN=0 and
XLSWAP=0
Set the Reference Divider input to select the VCXO
via REFDSRC
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF and PDFBK
Set the Reference Divider (N
REFDIV[11:0]
Set the Feedback Divider input to select the VCO via
FBKDSRC
Set the Feedback Divider (N
FBKDIV[14:0]
Set N
Divider modulus of N
POST2[1:0], and POST3[1:0].
Select the internal loop filter via EXTLF
Set VCOSPD=0 to select the VCO high speed range
Example Programming
P1
=1, N
P2
=3, and N
Px
=3 via POST1[1:0],
P3
=1 for a combined Post
FS6131-01
FS6131-01
FS6131-01
FS6131-01
F
R
) to a modulus of 8 via
) to a modulus of 3 via