11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 34

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
13.0
Line-locked clock generation, as used here, refers to the
process of synthesizing a clock frequency that is some
integer multiple of the horizontal line frequency in a
graphics system. The FS6131 is easily configured to
perform that function, as shown in Figure 31.
A line reference signal (f
for direct application to the Main Loop PFD. The Feed-
back Divider (N
of output clocks per line.
The source for the Feedback Divider is selected to be the
output of the Post Divider (N
output clock maintain a consistent phase alignment with
the line reference signal. The modulus of the Post Divider
should be selected to maintain a VCO frequency that is
comfortably within the operating range noted in Table 16.
Figure 31: Block Diagram: Line-Locked Clock Generation
Reference
HSYNC
(optional)
XOUT
FBK
SDA
REF
SCL
XTUNE
(optional)
XIN
Device Application:
Line-Locked Clock Generation
ADDR
F
) is programmed for the desired number
REFDSRC
Interface
(f
REF
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
HSYNC
Reference
REFDIV[11:0]
Divider
(N
) is applied to the REF input
Px
R
)
) so that the edges of the
Registers
Control
Divider
VCXO
ROM
PDREF
PDFBK
Frequency
XLROM[2:0]
Detector
Phase-
Frequency
Detector
Phase-
XLPDEN,
Divider
XLSWAP
Feedback
FBKDIV[14:0]
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
)
DOWN
UP
34
Charge
XLCP[1:0]
Pump
FBKDSRC[1:0]
13.1
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
Suppose that we wish to reconstruct the pixel clock from
a VGA source. This is a typical requirement of an LCD
projection panel application.
First, establish the total number of pixel clocks desired
between horizontal sync (HSYNC) pulses. The number of
pixel clocks is known as the horizontal total, and the
Feedback Divider is programmed to that value. In this
example, choose the horizontal total to be 800.
Next, establish the frequency of the HSYNC pulses
(f
this case, let f
f
CLK
HSYNC
f
Controlled
Oscillator
CLK
Voltage
is calculated to be:
OSCTYPE
VCOSPD,
) on the line reference signal for the video mode. In
Example Calculation
f
HSYNC
(f
HSYNC
VCO
OM[1:0]
)
MAIN LOOP
N
Gobbler
=31.5kHz. The output clock frequency
EXTLF
Clock
F
GBL
Internal
Loop
Filter
LFTC
31
5 .
POST3[1:0],
POST2[1:0],
POST1[1:0]
Divider
(N
Post
kHz
Px
)
Detect
STAT[1:0]
FS6131
Lock
800
CMOS/PECL
Output
CMOS
25
.
175
C
R
LF
LF
MHz
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
(f
IPRG
CLK
)