11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 36

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
14.0
Genlocking refers to the process of synchronizing the
horizontal sync pulses (HSYNC) of a target graphics
system to the HSYNC of a source graphics system. In a
genlocked mode, the FS6131 increases (or decreases)
the frequency of the VCO until the FBK input is frequency
matched and phase-aligned to the frequency applied to
the REF input. Since the feedback divider is within the
graphics system and the graphics system is the source of
the signal applied to the FBK input of the FS6131, the
graphics system is effectively synchronized to the REF
input as shown in Figure 32.
To configure the FS6131 for genlocking, the REF input
(pin 12) and the FBK input (pin 13) are switched directly
onto the feedback input of the PFD. The Reference and
Feedback dividers are not used.
Figure 32: Block Diagram: Genlocking
Reference
HSYNC
(optional)
XOUT
FBK
SDA
REF
SCL
XTUNE
(optional)
XIN
Device Application: Genlocking
ADDR
REFDSRC
Interface
(f
CLK
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Reference
REFDIV[11:0]
Divider
(N
R
)
Registers
Control
Divider
System HSYNC
VCXO
ROM
PDREF
PDFBK
Frequency
XLROM[2:0]
Detector
Phase-
Frequency
Detector
Phase-
XLPDEN,
Divider
XLSWAP
Feedback
FBKDIV[14:0]
Video Graphics System
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
)
DOWN
UP
Charge
XLCP[1:0]
Pump
FBKDSRC[1:0]
36
The output clock frequency is:
The only remaining task is to select a Post Divider
modulus (N
its nominal range.
14.1
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection
panel system to a VGA card-generated HSYNC. The total
number of pixel clocks generated by the VGA card,
known as the horizontal total, are 800. Therefore, the
LCD panel graphics system that is clocked by the
FS6131 is set to divide the output clock frequency (f
by 800. The input HSYNC reference frequency (f
15kHz.
Controlled
Oscillator
Voltage
OSCTYPE
VCOSPD,
Example Calculation
(f
f
VCO
Px
CLK
OM[1:0]
Clock In
)
) that allows the VCO frequency to be within
Gobbler
EXTLF
Clock
MAIN LOOP
GBL
Internal
Loop
Filter
LFTC
f
HSYNC
POST3[1:0],
POST2[1:0],
POST1[1:0]
Divider
(N
Post
Px
)
horizontal
Detect
STAT[1:0]
FS6131
Lock
CMOS/PECL
Output
CMOS
total
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
IPRG
(f
(f
CLK
CLK
HSYNC
)
)
CLK
) is
)