11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 2

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
DO = Digital Output; P = Power/Ground; # = Active Low pin
4.0
4.1
The Main Loop Phase Locked Loop (ML-PLL) is a stan-
dard phase- and frequency- locked loop architecture. As
shown in Figure 2, the ML-PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), a Feedback Divider, and a Post Divider.
During operation, the reference frequency (f
ated by either the on-board crystal oscillator or an exter-
nal frequency source, is first reduced by the Reference
Divider. The integer value that the frequency is divided by
is called the modulus, and is denoted as N
erence Divider. The divided reference is then fed into the
PFD.
The PFD controls the frequency of the VCO (f
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the ML-PLL. The output of the
VCO is fed back to the PFD through the Feedback Di-
vider (the modulus is denoted by N
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Main Loop PLL
Functional Block Description
TYPE
DIO
DIO
AO
DO
DO
DI
DI
AI
AI
AI
DI
DI
P
P
P
P
LOCK/IPRG
XTUNE
EXTLF
NAME
ADDR
XOUT
CLKP
CLKN
VDD
VDD
SDA
VSS
VSS
REF
FBK
SCL
XIN
F
) to close the loop.
U
= Input with Internal Pull-Up; DI
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit (see Section 5.2.1)
Ground
VCXO Feedback
VCXO Drive
VCXO Tune
Power Supply (+5V)
Lock Indicator / PECL Current Drive Programming
External Loop Filter
Ground
Reference Frequency Input
Feedback Input
Power Supply (+5V)
Differential Clock Output (+)
Differential Clock Output (-)
R
REF
for the Ref-
), gener-
VCO
)
2
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
If the VCO frequency is used as the PLL output fre-
quency (f
ten as
4.1.1
The Reference Divider is designed for low phase jitter.
The divider accepts either the output of either the Crystal
Loop (the VCXO output) or an external reference fre-
quency, and provides a divided-down frequency to the
PFD. The Reference Divider is a 12-bit divider, and can
be programmed for any modulus from 1 to 4095. See
both Table 3 and Table 8 for additional programming in-
formation.
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
CLK
Reference Divider
) then the basic PLL equation can be rewrit-
DESCRIPTION
f
CLK
f
N
VCO
F
f
REF
f
N
æ
ç ç
è
REF
R
N
N
F
R
.
ö
÷ ÷
ø
.