11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 27

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

10.4.1
The Device Mode block presets the demo program to
program the FS6131 either as a frequency synthesizer (a
stand alone clock generator) or as a line-locked or gen-
lock clock generator.
Frequency Synthesis: For use as a stand alone clock
generator. Note that the Reference Source is the on-chip
crystal oscillator, the expected crystal frequency is
27MHz, and the Voltage Tune in the Crystal Oscillator
(i.e. the VCXO) is disabled. The default output frequency
(CLK freq.) requested is 100MHz, with a maximum error
of 10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode.
Line-Locked/Genlock: For use in a line lock or genlock
application. Note that the Reference Source is the REF
Pin, and that the expected reference frequency is 8kHz.
The default output frequency requested is a 100x multiple
of the reference frequency.
10.4.2
By default the demo program assumes the FS6131 is
configured as a stand alone clock generator. Note that
the Reference Source defaults to the on-chip crystal os-
cillator, the expected crystal frequency is 27MHz, and the
Voltage Tune in the Crystal Oscillator block (i.e. the
VCXO) is disabled. The default output frequency (CLK
freq.) requested is 100MHz, with a maximum error of
10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode. The Loop Filter block is set to internal,
and the Check Loop Stability switch is on.
As an exercise, click on Calculate Solutions. The pro-
gram takes into account all of the screen settings and
calculates all possible combinations of Reference, Feed-
back, and Post Divider values that will generate the out-
put frequency (100MHz) from the input frequency
(27MHz) within the desired tolerance (10ppm).
A box will momentarily appear: “Calculating Solutions:
Press cancel to stop with the solutions calculated so far.”
A number in the box will increment for every unique solu-
tion that is found. This example will create six unique so-
lutions, which are then displayed in a window in the lower
right portion of the program screen.
Device Mode
Example: Frequency Synthesizer Mode
27
The best PLL performance is obtained by running the
VCO at as high a speed as possible. The last three solu-
tions show a VCO speed of 200MHz. Furthermore, good
PLL performance is obtained with the smallest dividers
possible, which means solution #4 should provide the
best results.
Figure 21: Frequency Synthesizer Screen
Clicking on Solution #4 highlights the row, and clicking on
Disp/Save Register Values provides a window with the
final values of key settings. A click on OK then displays a
second window containing register information per the
Register Map. If the solutions are to be saved to a file,
two formats are available: a text format for viewing, and a
data format for loading into the FS6131.
Clicking on Load Solution into Hardware (if enabled)
sends the information in an I
the parallel port. Note: This option is not available under
the Windows NT operating system.
If your operating system can support parallel port com-
munication but the connection cable is not attached, an
error message is displayed: "The FS6131 Hardware was
not detected! "Make sure that it is connected to the LPT#
printer port and that it is properly connected to a +5Volt
power supply."
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
2
C format to the FS6131 via
FS6131-01
FS6131-01
FS6131-01
FS6131-01