FAN3225T Fairchild Semiconductor, FAN3225T Datasheet - Page 2
FAN3225T
Manufacturer Part Number
FAN3225T
Description
The FAN3223-25 family of dual 4A gate drivers is designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN3224C.pdf
(25 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FAN3225TMPX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
FAN3225TMX
Manufacturer:
ON/安森美
Quantity:
20 000
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.8
Ordering Information
FAN3223CMPX
FAN3223CMX
FAN3223TMPX
FAN3223TMX
FAN3224CMPX
FAN3224CMX
FAN3224TMPX
FAN3224TMX
FAN3225CMPX
FAN3225CMX
FAN3225TMPX
FAN3225TMX
Package Outlines
Thermal Characteristics
8-Lead 3x3mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1.
2.
3.
4.
5.
6.
Part Number
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (
thermal pad) that are typically soldered to a PCB.
Theta_JT (
held at a uniform temperature by a top-side heatsink.
Theta_JA (Θ
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (
application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (
the center of the top of the package for the thermal environment defined in Note 4.
Figure 2. 3x3mm MLP-8 (Top View)
JB
JT
): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
JL
JT
JA
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
Dual Inverting Channels + Dual Enable
Dual Non-Inverting Channels + Dual
Enable
Dual Channels of Two-Input / One-
Output Drivers
Package
Logic
(1)
2
Threshold
CMOS
CMOS
CMOS
Input
TTL
TTL
TTL
1.2
38
JL
(2)
Figure 3. SOIC-8 (Top View)
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
64
29
JT
Package
(3)
JA
42
87
(4)
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Packing
2.8
Method
JB
41
(5)
0.7
2.3
JT
www.fairchildsemi.com
(6)
Quantity
per Reel
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
Units
°C/W
°C/W