FAN5355 Fairchild Semiconductor, FAN5355 Datasheet - Page 17

• Manufacturer Part Number: FAN5355
• Description: The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.0
Circuit Description
Overview
The FAN5355 is a synchronous buck regulator that typically
operates at 3MHz with moderate to heavy load currents. At
light load currents, the converter operates in power-saving
PFM mode. The regulator automatically transitions between
fixed-frequency PWM and variable-frequency PFM mode to
maintain the highest possible efficiency over the full range of
load current.
The FAN5355 uses a very fast non-linear control architecture
to achieve excellent transient response with minimum-sized
external components.
The FAN5355 integrates an I
transfers up to 3.4Mbps. This communication interface can be
used to:
1.
2.
3.
4.
5.
For more details, refer to the I
Description sections.
Output Voltage Programming
Option
where N
register that controls V
Note:
11. Option 02 and 08 maximum voltage is 1.4375V (see
00, 02, 03, 08
Dynamically re-program the output voltage in 12.5mV
increments.
Reprogram the mode of operation to enable or disable
PFM mode.
Control voltage transition slew rate.
Control the frequency of operation by synchronizing to an
external clock.
Enable / disable the regulator.
Table 3).
06
(11)
VSEL
is the decimal value of the setting of the VSEL
V
V
V
OUT
OUT
OUT
Equation
OUT


. 1
. 0
.
75
1875
2
C-compatible interface, allowing

N

VSEL
2
N
C Interface and Register
VSEL

12

12
5 .
mV
5 .
mV
(1)
(2)
17
Power-Up, EN, and Soft-Start
All internal circuits remain de-biased and the IC is in a very
low quiescent-current state until the following are true:
1.
2.
At that point, the IC begins a soft-start cycle, its I
enabled, and its registers are loaded with their default values.
During the initial soft start, V
programmed in the VSEL register selected by the VSEL pin.
The soft start features a fixed output-voltage slew rate of
18.75V/ms and achieves regulation approximately 90s after
EN rises. PFM mode is enabled during soft start until the
output is in regulation, regardless of the MODE bit settings.
This allows the regulator to start into a partially charged output
without discharging it; in other words, the regulator does not
allow current to flow from the load back to the battery.
As soon as the output has reached its set point, the control
forces PWM mode for about 85s to allow all internal control
circuits to calibrate.
Symbol Description
Table 2. Soft-Start Timing (see Figure 37)
t
SSDLY
t
t
REG
POK
V
EN is HIGH.
IN
is above its rising UVLO threshold, and
Time from EN to start of
soft-start ramp
V
start to
regulation
PWROK (CONTROL2[5])
rising from end of t
regulator stays in PWM
mode during this time
OUT
Figure 37. Soft-Start Timing
ramp
Opt 03, 06
Opt 00,
02, 08
OUT
REG
ramps linearly to the set point
and
16 +(VSEL–0.7) X 53
(VSEL–0.1) X 53
www.fairchildsemi.com
Value (s)
2
C interface is
75
10