FDMF6705B Fairchild Semiconductor, FDMF6705B Datasheet - Page 13

• Manufacturer Part Number: FDMF6705B
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 26
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 turns off after a propagation delay (t
Once the GL pin is discharged below ~1V, Q1 turns on
after adaptive delay, t
VSWH
VSWH
PWM
GH
GL
to
Notes:
t
t
PWM
t
t
t
SMOD#
t
t
V
PD_xxx
D_xxx
PD_PHGLL
PD_PLGHL
PD_PHGHH
PD_SLGLL
PD_SHGLH
IH_PWM
= delay from IC generated signal to IC generated signal.
= propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
= SMOD# fall to LS V
t
= PWM rise to LS V
= PWM fall to HS V
CCM
= SMOD# rise to LS V
= PWM rise to HS V
PD_PHGLL
t
D_DEADON
1.0V
90%
t
PD_PLGHL
GS
GS
GS
GS
fall, V
fall, V
GS
fall, V
rise, V
D_DEADON
V
rise, V
t
IL_PWM
D_DEADOFF
IH_PWM
IL_PWM
IL_SMOD
IH_PWM
t
IH_SMOD
2.2V
R_GL
to 90% HS V
to 90% LS V
to 90% LS V
10%
to 10% HS V
t
.
less than
to 10% LS V
D_HOLD - OFF
Figure 26. PWM and 3-StateTiming Diagram
GS
GS
GS
GS
GS
t
D_HOLD - OFF
(SMOD# held LOW)
Enter
3 -State
Example (t
t
F_GL
DCM
PD_PHGLL
V
D_DEADON
IH_PWM
Exit
3-State
t
t
R_GH
– LS V
PD_TSGHH
).
GS
13
(GL) LOW to HS V
Exiting 3-state
t
t
Dead Times
t
t
PD_TSGHH
PD_TSGLH
D_DEADON
D_DEADOFF
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the VSWH pin. When the PWM signal goes
LOW, Q1 turns off after a propagation delay (t
Once the VSWH pin falls below ~2.2V, Q2 turns on after
adaptive delay, t
monitored. When V
secondary adaptive delay is initiated, which results in
Q2 being driven on after t
state. This function is implemented to ensure C
recharged each switching cycle in the event that the SW
voltage does not fall below the 2.2V adaptive threshold.
Secondary delay t
t
D_HOLD -OFF
V
Example (t
TRI_HI
= PWM 3-state to LOW to LS V
= PWM 3-state to HIGH to HS V
3 -State
= LS V
= VSWH fall to LS V
Enter
t
F_GH
GS
GS
PD_PHGLL
fall to HS V
(GH) HIGH)
DCM
– PWM going HIGH to LS V
V
IH_PWM
GS
GS
t
D_TIMEOUT
rise, LS-comp trip value (~1.0V GL) to 10% HS V
rise, SW-comp trip value (~2.2V VSWH) to 10% LS V
PD_TSGHH
Exit
3 State
D_DEADOFF
GS(Q1)
GS
GS
rise, V
rise, V
is discharged below ~1.2V, a
t
less than
is longer than t
D_HOLD - OFF
D_TIMEOUT
IL_PWM
. Additionally, V
IH_PWM
GS
(GL) going LOW)
to 10% LS V
to 10% HS V
t
, regardless of SW
D_HOLD -OFF
3 -State
Enter
GS
GS
D_DEADOFF
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t
PD_TSGLH
3-State
Exit
PD_PLGHL
GS
GS(Q1)
V
V
V
V
BOOT
IH PWM
TRI_LO
GS
TRI_HI
IL_PWM
V
V
90%
10%
.
90%
10%
OUT
IN
is
is
).