71M6533G Maxim, 71M6533G Datasheet - Page 97
71M6533G
Manufacturer Part Number
71M6533G
Description
The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6533.pdf
(132 pages)
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5.3.5 CE Calculations
* Only EQU = 5 is supported by CE code version CE34A02D.
5.3.6 CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through B as shown in
Table
Rev 2
EQU[
2:0]
0*
1*
2*
3*
4*
5
IA FIR data
VA FIR data
IB FIR data
VB FIR data
IC FIR data
VC FIR data
ID FIR data
TEMP FIR data
VBAT FIR data
…
Chip ID, Version bytes
Last Address
56.
VA IA
(1 element, 2W
1φ)
VA*(IA-IB)/2
(1 element, 3W
1φ)
VA*IA + VB*IB
(2 element, 3W
3φ Delta)
VA*(IA-IB)/2 +
VC*IC
(2 element, 4W
3φ Delta)
VA*(IA-IB)/2 +
VB*(IC-IB)/2
(2 element, 4W
3φ Wye)
VA*IA + VB*IB
+ VC*IC
(3 element, 4W
3φ Wye)
(WSUM/VARS
Watt & VAR
Formula
Name
UM)
Table 55: CE EQU[2:0] Equations and Element Input Mapping
Element Input Mapping
0x3FF
0x0A
0x0B
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
W0SUM/ VAR0SUM
CE
Table 56: CE Raw Data Access Locations
VA*(IA-IB)/2
VA*(IA-IB)/2
VA*(IA-IB)/2
VA*IA
VA*IA
VA*IA
Address
0xFFC
003C
0x0C
0x2C
MPU
0x00
0x04
0x08
0x10
0x14
0x18
0x28
…
…
Internal …
Internal …
Internal Last Memory Location
Type
Read
Input
Input
Input
Input
Input
Input
Input
Input
Input
Only
VB*(IC-IB)/2
VAR1SUM
Description
ADC Input data, valid at the end of the MUX
frame. The address mapping of analog
inputs to memory is hard-wired in the ADC
converter circuit.
Upper 16 bits are zero. Lower 16 bits are
CHIP_ID[15:8], VERSION[7:0]. This word is
read only.
W1SUM/
VB*IB
VB*IB
–
–
–
VAR2SUM
W2SUM/
VC*IC
VC*IC
–
–
–
–
I0SQ
SUM
IA-IB
IA-IB
IA-IB
IA
IA
IA
I1SQ
SUM
IC-IB
IB
IB
IB
IB
–
I2SQ
SUM
IC
IC
IC
–
–
–
97
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