71M6533G Maxim, 71M6533G Datasheet - Page 48

• Manufacturer Part Number: 71M6533G
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

Three-wire (µ-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 2. The EECTRL bits when the three-wire interface is selected are
shown in
or read from the EEPROM, depending on the values of the EECTRL bits.
The timing diagrams in
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
48
Control
Status
Bit
3:0
Bit
7
6
5
4
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too
busy to process interrupts.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In
this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the
speed at which the SDA pin can be switched from output to input. However, controlling DIO4 and
Table
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
CNT[3:0]
Name
Name
BUSY
WFR
HiZ
RD
45. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
Read/
Read/
Figure 10
Write
Write
W
W
W
W
R
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
Reset
State
through
Table 45: EECTRL Bits for the 3-wire Interface
Polarity
Figure 14
Description
describe the 3-wire EEPROM interface behavior. All
0110
1001
Others
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
Figure 10
through
Figure 14
Rev 2