71M6533G Maxim, 71M6533G Datasheet - Page 43
71M6533G
Manufacturer Part Number
71M6533G
Description
The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6533.pdf
(132 pages)
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On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO.
Once a pin is configured as DIO, it can be configured independently as an input or output with the
DIO_DIR bits or the LCD_SEGn registers. Input and output data are written to or read from the pins using
SFR registers P0, P1, and P2.
Table 39
Table 42
entries marked with an asterisk and grayed are applicable to the 71M6534 only.
Rev 2
Configuration (DIO
or LCD segment)
Data Register
Direction Register
0 = input, 1 = output
Configuration (DIO
or LCD segment)
Data Register
Direction Register
0 = input, 1 = output
Internal Resources
Configurable
71M6533 Pin #
71M6534 Pin #
71M6533 Pin #
71M6534 Pin #
LCD Segment
LCD Segment
DIO
DIO
through
shows all the DIO pins with their configuration, direction control and data registers. Table
Table 40: Data/Direction Registers and Internal Resources for DIO 16-30
Table 39: Data/Direction Registers and Internal Resources for DIO 1-15
LCD_BITMAP[39:32]
114 109
PB
97
16
36
33
39
0
–
Y
–
4
0
0
Always DIO
91
17
37
12
17
Y
1
–
5
1
1
1
1
DIO0 = P0 (SFR 0x80)
DIO_DIR0 (SFR 0xA2)
DIO2 = P2 (SFR 0xA0)
DIO_DIR2 (SFR 0xA1)
18
38
13
18
Y
2
–
3
3
2
2
6
2
2
22
19
39
64
74
17
Y
3
–
3
3
7
3
3
0
24
60
70
20
40
65
75
Y
4
4
4
0
4
4
25
61
71
1
21 22* 23
41 42* 43
66
76 115 64
Y
5
5
5
1
5
5
LCD_BITMAP[47:40]
LCD_BITMAP[31:24]
26
62
72
2
2*
6*
6*
Y
6
6
6
–
27
63
73
3
54
Y
7
7
7
3
7
7
28
67
77
4
24
44
46
52
Y
8
0
0
4
0
29
68
78
5
25
45
43
49
Y
9
1
1
5
1
DIO1 = P1 (SFR 0x90)
DIO3 = P3 (SFR 0xB0)
DIO_DIR1 (SFR 0x91)
10
30
69
79
6
26
46
42
48
Y
2
2
6
2
11 12* 13
31 32* 33
70
80 120 50
7
27 28* 29
47 48* 49
41
47
Y
3
3
7
3
LCD_BITMAP[55:48]
LCD_BITMAP[39:32]
0*
81
0*
4*
4*
4*
–
–
–
44
1
32
38
5
5
–
1
5
14
34
29
35
2
30
50
35
41
6
6
–
2
6
15
35
30
36
3
7
7
–
–
–
–
–
–
43
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