STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 61

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
8.1.4
8.1.5
Note:
Table 24.
Reset
A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or
the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:
●
●
●
nBOOTMODE
nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset
(NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is
asserted (pulled or driven low) when coming out of reset, the processor starts executing an
embedded serial boot loader instead of its normal program.
While in reset and during the subsequent power-on-reset startup delay (512 high-frequency
RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At
the end of this time, the STM32W108 samples nBOOTMODE: a high level selects normal
startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5
is configured as a floating input. The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register
captures the state of nBOOTMODE so that software may act on this signal if required.
To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed
252 pF.
GPIO
PC0
PC2
PC3
PC4
PC4
PA7
The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.
The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the
normal configuration for PA7.
The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial
Wire/JTAG access to override the normal configuration of PC0, PC2, PC3, and PC4.
GPIO_EXTREGEN bit set in the
GPIO_DBGCFG register
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in Serial Wire
mode
GPIO forced functions
Override condition
Doc ID 16252 Rev 13
Open-drain output
Input with pull up
Push-pull output
Input with pull up
Input with pull up
Bidirectional (push-pull
output or floating input)
controlled by debugger
interface
Forced function
General-purpose input/outputs
Forced signal
REG_EN
SWDIO
JTDO
JTMS
JRST
JDTI
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