STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 175

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
11.1.5
11.1.6
DMA
The ADC DMA channel writes converted data, which incorporates the offset/gain correction,
into a DMA buffer in RAM.
The ADC DMA buffer is defined by two registers:
●
●
To prepare the DMA channel for operation, reset it by writing the ADC_DMARST bit in the
ADC_DMACFG register, then start the DMA in either linear or auto wrap mode by setting
the ADC_DMALOAD bit in the ADC_DMACFG register. The ADC_DMAAUTOWRAP bit in
the ADC_DMACFG register selects the DMA mode: 0 for linear mode, 1 for auto wrap mode.
●
●
When the DMA fills the lower and upper halves of the buffer, it sets the INT_ADCULDHALF
and INT_ADCULDFULL bits, respectively, in the INT_ADCFLAG register. The current
location to which the DMA is writing can also be determined by reading the ADC_DMACUR
register.
ADC configuration register
The ADC configuration register (ADC_CFG) sets up most of the ADC operating parameters.
Input
The analog input of the ADC can be chosen from various sources. The analog input is
configured with the ADC_MUXP and ADC_MUXN bits within the ADC_CFG register.
Table 108
Table 108. ADC inputs
ADC_MUXn
ADC_DMABEG is the start address of the buffer and must be even.
ADC_DMASIZE specifies the size of the buffer in 16-bit samples, or half its length in
bytes.
In linear mode the DMA writes to the buffer until the number of samples given by
ADC_DMASIZE has been output. Then the DMA stops and sets the
INT_ADCULDFULL bit in the INT_ADCFLAG register. If another ADC conversion
completes before the DMA is reset or the ADC is disabled, the INT_ADCOVF bit in the
INT_ADCFLAG register is set.
In auto wrap mode the DMA writes to the buffer until it reaches the end, then resets its
pointer to the start of the buffer and continues writing samples. The DMA transfers
continue until the ADC is disabled or the DMA is reset.
0
1
2
3
4
5
6
7
8
shows the possible input selections.
(1)
Analog source at ADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
No connection
No connection
GND
Doc ID 16252 Rev 13
PB5
PB6
PB7
PC0
PA4
PA5
Internal connection Calibration
GPIO pin
Analog-to-digital converter
Purpose
175/232