STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 100

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
9.9.5
Table 60.
9.10
9.11
9.11.1
Table 61.
100/232
31
15
31
15
30
14
30
14
Bits [3:0]
Serial clock exponential prescaler register (SCx_RATEEXP)
Address offset: 0xC864 (SC1_RATEEXP) and 0xC064 (SC2_RATEEXP)
Reset value:
Serial clock exponential prescaler register (SCx_RATEEXP)
SPI slave mode registers
Refer to
SCx_DATA, SCx_SPICFG, and SCx_SPISTAT registers.
Inter-integrated circuit (I
I
Address offset: 0xC844 (SC1_TWISTAT) and 0xC044 (SC2_TWISTAT)
Reset value:
I
2
2
Bit 3
Bit 2
Bit 1
Bit 0
C status register (SCx_TWISTAT)
C status register (SCx_TWISTAT)
29
13
29
13
SC_RATEEXP: The exponential component (EXP) of the clock rate in the equation:
SC_TWICMDFIN: This bit is set when a START or STOP command completes. It clears on the
next I2C bus activity.
SC_TWIRXFIN: This bit is set when a byte is received. It clears on the next I
SC_TWITXFIN: This bit is set when a byte is transmitted. It clears on the next I
SC_TWIRXNAK: This bit is set when a NACK is received from the slave. It clears on the next
I
2
C bus activity.
Rate = 12 MHz / ( (LIN + 1) * (2^EXP) )
28
12
28
12
Section 9.9: SPI master mode registers on page 97
27
11
27
11
0x0000 0000
0x0000 0000
26
10
26
10
Reserved
Reserved
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
25
25
9
9
Doc ID 16252 Rev 13
24
24
8
8
Reserved
Reserved
2
C) interface registers
23
23
7
7
22
22
6
6
21
21
5
5
for a description of the
20
20
4
4
WICM
SC_T
DFIN
19
19
3
3
r
WIRXF
SC_T
SC_RATEEXP
18
18
IN
2
2
2
r
C bus activity.
2
rw
C bus activity.
WITXF
SC_T
17
17
IN
1
1
r
WIRXN
SC_T
AK
16
16
0
0
r