P8XC557E4 NXP Semiconductors, P8XC557E4 Datasheet - Page 41

• Manufacturer Part Number: P8XC557E4
• Description: The P80C557E4/P83C557E4/P89C557E4 (hereafter generically referred to as P8xC557E4) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family
• Manufacturer: NXP Semiconductors

1. In Idle Mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0) these pins are in a
Philips Semiconductors
Table 39. Description of PCON bits
6.11 Power Reduction Modes
Two software-selectable modes of reduced power consumption are
implemented. These are the Idle Mode and the Power-down Mode.
Idle Mode operation permits the interrupt, serial ports and timer
blocks T0, T1 and T3 to function while the CPU is halted. The
following functions are switched off when the microcontroller enters
the Idle Mode:
Table 40. External Pin Status During Idle and Power-Down Modes
NOTE:
1999 Mar 02
Idle
Idle
Power-down
Power-down
CPU
Timer 2
PWM0, PWM1
ADC
Single-chip 8-bit microcontroller
high-impedance state.
SYMBOL
SMOD
MODE
ARD
WLE
GF1
GF0
RFI
IDL
PD
PCON (87H)
MEMORY
External
External
Internal
Internal
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
(halted)
(stopped and reset)
(reset, output = HIGH)
(aborted if conversion in progress)
BIT
ALE
1
1
0
0
SMOD
Double Baud rate bit. When set to logic 1 the baud rate is doubled when the serial port SIO0 is being used in
modes 1, 2, or 3.
AUX-RAM disable bit. When set to a 1 the internal 768 bytes AUX-RAM is disabled, so that all
MOVX-Instructions access the external data memory – as it is with the standard PCB80C51.
Reduced radio frequency interference bit. When set to a 1 the toggling of ALE pin is prohibited. This bit is
cleared on RESET (see also sections Features (EMC) and Pinning).
Watchdog load enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is cleared
when timer T3 is loaded.
General-purpose flag bit
General-purpose flag bit
Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high.
Idle Mode bit. Setting this bit activates the Idle Mode.
7
PSEN
1
1
0
0
ARD
6
Figure 39. Power control register (PCON).
PORT 0
high-Z
high-Z
data
data
RFI
5
PORT 1
data
data
data
data
41
WLE
PORT 2
address
P83C557E4/P80C557E4/P89C557E4
4
The following functions remain active during Idle Mode. These
functions may generate an interrupt or reset and thus terminate the
Idle Mode:
In Power-down Mode the system clock is halted. If the PLL oscillator
is selected (SELXTAL1 = 0) and the RUN32 bit is set, the 32 kHz
oscillator keeps running, otherwise it is stopped. If the HF-oscillator
(SELXTAL1 = 1) is selected, it is stopped after setting the bit PD in
the PCON register.
data
data
data
Timer 0, Timer 1, Timer 3 (Watchdog timer)
UART
I
External interrupt
Seconds Timer
2
C
FUNCTION
PORT 3
GF1
3
data
data
data
data
PORT 4
GF0
data
data
data
data
2
operative (1)
operative (1)
SCL/SDA
high-Z
high-Z
PD
1
Product specification
PWM0/PWM1
IDL
0
HIGH
HIGH
HIGH
HIGH