P8XC557E4 NXP Semiconductors, P8XC557E4 Datasheet - Page 37

• Manufacturer Part Number: P8XC557E4
• Description: The P80C557E4/P83C557E4/P89C557E4 (hereafter generically referred to as P8xC557E4) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The polling cycle is repeated with every machine cycle, and the
values polled are the values present at S5P2 of the previous
machine cycle. Note that if an interrupt flag is active but is not being
responded to because of one of the above conditions, and if the flag
is inactive when the blocking condition is removed, then the blocked
interrupt will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered. Every polling
cycle is new.
The processor acknowledges an interrupt request by executing a
hardware-generated LCALL to the appropriate service routine. In
some cases it also clears the flag which generated the interrupt, and
in others it does not. It clears the Timer 0, Timer 1, and external
Table 33. Description of IEN0 bits
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
EAD
ES1
ES0
EX1
EX0
ET1
ET0
EA
IEN0 (A8H)
IEN0.7
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
BIT
EA
Global enable/disable control
0 =
1 =
Enable ADC interrupt
Enable SIO1 (I
Enable SIO0 (UART) interrupt
Enable Timer 1 interrupt
Enable External interrupt 1 / Seconds interrupt
Enable Timer 0 interrupt
Enable External interrupt 0
7
No interrupt is enabled
Any individually enabled interrupt will be accepted
EAD
6
Figure 34. Interrupt enable register (IEN0).
2
C) interrupt
ES1
5
37
ES0
P83C557E4/P80C557E4/P89C557E4
4
interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if
it was transition-activated. All other interrupt flags are not cleared by
hardware and must be cleared by the software. The LCALL pushes
the contents of the program counter on to the stack (but it does not
save the PSW) and reloads the PC with an address that depends on
the source of the interrupt being vectored to as shown in Table 38.
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the “priority
level active” flip-flop that was set when this interrupt was
acknowledged. It then pops the top two bytes from the stack and
reloads the program counter. Execution of the interrupted program
continues from where it was interrupted.
FUNCTION
ET1
3
EX1
2
ET0
1
Product specification
EX0
0