AD9739 Analog Devices, AD9739 Datasheet - Page 47

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
Table 32. Recommended SPI Initialization with SYNC Controller Enabled
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Address (Hex)
0x00
0x00
0x00
0x22
0x23
0x24
0x25
0x27
0x28
0x29
0x26
0x26
Not applicable
0x2A
0x15
0x10
0x10
0x10
Not applicable
0x21
0x0D
Not applicable
0x13
0x10
0x10
0x10
0x21
Not applicable
0x06, 0x07
0x08
Write Value
0x00
0x20
0x00
0x0F
0x0F
0x30
0x80
0x44
0x6C
0xCB
0x02
0x03
Not applicable
0x42
0x00
0x60 or 0x40
0x70 or 0x50
Not applicable
Not applicable
0x72
0x00
0x02
0x03
Not applicable
0x00, 0x02
0x00
Comments
Enable the mu controller search and track mode.
Disable sync controller before enabling it.
Enable sync controller:
Read back Register 0x21 to confirm proper operation:
Disable the data Rx controller before enabling it.
Enable the data Rx controller for loop and IRQ.
Wait for 135 K × 1/f
Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto
Bits[2:0] because the MSB/LSB format can be unknown at power-up.
Software reset to default SPI values.
Clear the reset bit.
Set the common-mode voltage of DACCLK_P and DACCLK_N inputs.
Configure the mu controller. Refer to Table 28 for recommended target Mu slope and
phase settings vs. clock rate.
Wait for 160 K × 1/f
Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop
is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three
before breaking out of the loop and reporting a mu lock failure.
Configure sync controller.
Enable sync controller for loop and IRQ.
0x60 = master mode.
0x40 = slave mode.
0x70 = master mode.
0x50 = slave mode.
Wait for 160 K × 1/f
0x90 = master mode.
0x00 = slave mode.
If not, proceed to Step 15 and repeat. Limit to three attempts before breaking out of
loop and reporting sync lock failure.
Read back Register 0x0D and confirm Bits[5:4] = 10. If not, proceed to Step 2 and repeat.
Limit to three attempts before breaking out of loop and reporting sync lock failure.
Ensure that the
Set FINE_DEL_SKEW to 2.
Enable the data Rx controller for search and track mode.
Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop
is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat.
Limit attempts to three before breaking out of the loop and reporting an Rx data lock
failure.
Readback DCI_DEL value in Register 0x13 and Register 0x14 for master and. If slave
devices are not within 40 codes of each other, re-specify target DCI_DEL value to be
average between master and readback DCI_DEL value.
Optional: modify the TxDAC I
Optional: modify the TxDAC operation mode (the default is normal mode).
Rev. B | Page 47 of 48
AD9739
DATA
DATA
DATA
cycles.
for DLL to lock.
cycles.
is fed with DCI clock input from the data source.
OUTFS
setting (the default is 20 mA).
AD9739