AD9739 Analog Devices, AD9739 Datasheet - Page 32

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9739
MU CONTROLLER
A delay lock loop (DLL) is used to optimize the timing between
the internal digital and analog domains of the
data is successfully transferred into the TxDAC core at rates of
up to 2.5 GSPS. As shown in Figure 48, the DAC clock is split
into an analog and a digital path with the critical analog path
leading to the DAC core (for minimum jitter degradation) and
the digital path leading to a programmable delay line. Note that
the output of this delay line serves as the master internal digital
clock from which all other internal and external digital clocks
are derived. The amount of delay added to this path is under the
control of the mu controller, which optimizes the timing between
these two clock domains and continuously tracks any variation
(once in track mode) to ensure proper data hand-off.
The mu controller adjusts the timing relationship between the
digital and analog domains via a tapped digital delay line having
a nominal total delay of 864 ps. The delay value is programmable
to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL
register, resulting in a nominal resolution of 2 ps/LSB. Because a
time delay maps to a phase offset for a fixed clock frequency,
the control loop essentially compares the phase relationship
between the two clock domains and adjusts the phase (that is, via a
tapped delay line) of the digital clock such that it is at the desired
fixed phase offset (SET_PHS) from the critical analog clock.
CLOCK
DAC
18
16
14
12
10
8
6
4
2
0
Figure 49. Typical Mu Phase Characteristic Plot at 2.4 GSPS
0
GUARD
DESIRED
PHASE
BAND
40
Figure 48. Mu Delay Controller Block Diagram
14-BIT
DATA
80
SEARCH STARTING
120
LOCATION
DELAY
MU
160
CIRCUITRY
CONTROLLER
DIGITAL
DELAY
MU DELAY
200
MU
240
14-BIT
DATA
DETECTOR
PHASE
280
CIRCUITRY
320
ANALOG
AD9739
360
GUARD
400
BAND
IOUTP
IOUTN
such that
440
Rev. B | Page 32 of 48
Figure 49 maps the typical mu phase characteristic at 2.4 GSPS vs.
the 9-bit digital delay setting (MUDEL). The mu phase scaling
is such that a value of 16 corresponds to 180 degrees. The critical
keep-out window between the digital and analog domains occurs
at a value of 0 (but can extend out to 2 depending on the clock
rate). The target mu phase (and slope) is selected to provide
optimum ac performance while ensuring that the mu controller
for any device can establish and maintain lock. For example,
while a slope and phase setting of −6 is considered optimum
for operation between 1.6 GSPS and 2.5 GSPS, other values are
required below 1.6 GSPS.
The mu phase characteristics can vary significantly among devices
due to gm variations in the digital delay line that are sensitive to
process skews (along with temperature and supply). As a result,
careful selection of the target phase location is required such
that the mu controller can converge upon this phase location
for all devices. Figure 50 shows that mu phase characteristics of
three devices at 25°C from slow, nominal, and fast skew lots at
1.2 GSPS. Note that a −6 mu phase setting does not map to any
delay line tap setting for the fast process skew case; therefore,
another target mu phase is recommended at this clock rate.
Table 28 provides a list of recommended mu phase/slope settings
over the specified clock range of the
considerations previously described. These values should be
used to ensure robust operation of the mu controller.
Table 28. Recommended Target Mu Phase Settings vs. Clock Rate
Clock Rate (GSPS)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6 to 2.5
Figure 50. Mu Phase Characteristics of Three Devices from Different Process
18
16
14
12
10
8
6
4
2
0
0
NOM_P1
SLOW_P1
FAST_P1
40
80
120
160
Lots at 1.2 GSPS
DELAY LINE TAP
200
Slope
−
−
+
+
+
−
−
−
−
240
AD9739
280
320
based on the
Data Sheet
MU Phase
6
4
5
8
12
12
10
8
6
360
400
440