AD9739 Analog Devices, AD9739 Datasheet - Page 34

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9739
INTERRUPT REQUESTS
The
request output signal (IRQ) that indicates that one or more of the
AD9739
controllers include the mu, data receiver, and synchronization
controllers. The host can then poll the IRQ status register
(Register 0x04) to determine which controller has lost lock.
The IRQ output signal is an active high output signal available
on Pin F13. If used, its output should be connected via a 10 kΩ
pull-up resistor to VDD33.
Each IRQ is enabled by setting the enable bits in Register 0x03,
which purposely has the same bit mapping as the IRQ status
bits in Register 0x04. Note that these IRQ status bits are set only
when the controller transitions from a false to true state. Therefore,
it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to
be set when a controller temporarily loses lock but is able to
reestablish lock before the IRQ is serviced by the host. In this
case, the host should validate the present status of the suspect
controller by reading back its current status bits, which are
available in Register 0x21 and/or Register 0x2A. Based on the
status of these bits, the host can take appropriate action, if required,
to reestablish lock. To clear an IRQ after servicing, it is necessary to
reset relevant bits in Register 0x03 by writing 0 followed by
another write of 1 to reenable. A detailed diagram of the
interrupt circuitry is shown in Figure 51.
DATA
SPI
AD9739
SCLK
internal controllers have achieved lock or lost lock. These
IMR
can provide the host processor with an interrupt
SOURCE
Figure 51. Interrupt Request Circuitry
INT
D
Q
INT(n)
SPI WRITE
DATA = 1
(PIN F13)
SPI ISR
READ DATA
SPI ADDRESS
INT
SOURCE
Rev. B | Page 34 of 48
It is also possible to use the IRQ during the
phase after power-up to determine when the mu and data receiver
controllers have achieved lock. For example, before enabling the
mu controller, the MU_LCK_EN bit (Register 0x03, Bit 2) can be
set and the IRQ output signal monitored to determine when lock
has been established before continuing in a similar manner with
the data receiver controllers. Note that the relevant LCK bit should
be cleared before continuing to the next controller. After all
controllers are locked, the lost lock enable bits (that is, x_LST_EN)
should be set.
Table 29. Interrupt Request Registers
Address (Hex)
0x03
0x04
0x21
0x2A
Bit
5
4
3
2
1
0
5
4
3
2
1
0
7
5
4
3
1
0
1
0
Description
SYNC_LST_EN
SYNC_LCK_EN
MU_LST_EN
MU_LCK_EN
RCV_LST_EN
RCV_LCK_EN
SYNC_LST_IRQ
SYNC_LCK_IRQ
MU_LST_IRQ
MU_LCK_IRQ
RCV_LST_IRQ
RCV_LCK_IRQ
SYNC_TRK_ON
SYNC_LST
SYNC_LCK
RCVR_TRK_ON
RCVR_LST
RCVR_LCK
MU_LST
MU_LKD
AD9739
Data Sheet
initialization