AD9739 Analog Devices, AD9739 Datasheet - Page 29

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
The div-by-4 circuit generates four clock phases that serve as inputs
to the data receiver controller. All of the DDR registers in the data
and DCI paths operate on both clock edges; however, for clarity
purposes, only the phases (that is, 0
the positive edge of each path are shown. One of the div-by-4
phases is used to generate the DCO signal; therefore, the phase
relationship between DCO and clocks fed into the controller
remains fixed. Note that it is this attribute that allows possible
factory calibration of images and clock spurs attributed to f
modulation of the critical DAC clock.
Once this data has been successively sampled into the first set
of registers, an elastic FIFO is used to transfer the data into
the
variation between the two clock domains, the data receiver
controller should always be enabled and placed into track
mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates
continuously in the background to track delay variations between
the host and
the DCI signal is sampled within a very narrow window defined
by two internally generated clocks (that is, PRE and PST), as
shown in Figure 43.
DBx[13:1]
AD9739
DCO
DCI
clock domain. To continuously track any phase
AD9739
DDR
DDR
DDR
DDR
FF
FF
clock domains. It does so by ensuring that
FF
FF
DCI WINDOW POST
DCI WINDOW SAMPLE
DCI WINDOW PRE
SAMPLE
DELAY
DELAY
DELAY
POST
FINE
FINE
FINE
PRE
o
and 90
DATA RECEIVER CONTROLLER
o
Figure 42. Top Level Diagram of the Data Receiver Controller
) corresponding to
ELASTIC FIFO
DDR
FF
DELAY
DELAY
DAC
Rev. B | Page 29 of 48
/4
DDR
FF
STATE MACHINE/
TRACKING LOOP
Proper sampling of the DCI signal can also be confirmed by
monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2)
and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings
are correct, the state of DCI_ PRE_PH0 should be 0, and the
state of DCI_PST_PH0 should be 1. Note that the states of these
status bits may toggle occasionally due to cycle-to cycle jitter
exceeding the window width. However, the controller averages
these status bits over multiple clock cycles to ensure that the
DCI signal falls within a programmable window.
The skew or window width (FINE_DEL_SKEW) is set via
Register 0x13, Bits[3:0], with a maximum skew of approximately
180 ps and resolution of 12 ps. It is recommended that the skew
be set to 36 ps (that is, Register 0x13 = 0x72) during initialization.
The skew setting also affects the speed of the controller loop,
with tighter skew settings corresponding to longer response time.
DCI DELAY
SAMPLE
DELAY
DELAY
DELAY
FINE DELAY
FINE DELAY
PRE
PST
Figure 43. Pre- and Post-Delay Sampling Diagram
DCI
SAMPLE
DDR
DELAY
FF
DELAY
PATH
PATH
DCI
FINE_DEL_SKEW
DATA TO
CORE
CONTROLLER
TO SYNC
FROM SYNC CONTROLLER
SPI REG 0x14, BIT[7:6]
180
DIV-BY-4
270
90
0
PHASE
ROTATION
DIV-BY-4
OR
AD9739
F
DAC