AD9739 Analog Devices, AD9739 Datasheet - Page 39

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
CLOCK INPUT CONSIDERATIONS
The quality of the clock source and its drive strength are
important considerations in maintaining the specified ac
performance. The phase noise and spur characteristics of the
clock source should be selected to meet the target application
requirements. Phase noise and spurs at a given frequency offset
on the clock source are directly translated to the output signal. It
can be shown that the phase noise characteristics of a reconstructed
output sine wave are related to the clock source by 20 × log10
(f
thermal and quantization effects, are negligible.
The
when driven by a fast slew rate originating from the LVPECL or
CML output drivers. For a low jitter sinusoidal clock source, the
ADCLK914
CML input signal for the
specifications and characterization presented in the data sheet
are with the
generator with the clock receiver biased at a 800 mV level. A
dc blocking capacitor is used between the clock driver output
and clock receiver input to allow for different dc bias levels.
To minimize signal loss for high clock rates, a high quality, dc
blocking RF capacitor is recommended.
Figure 60 shows a clock source based on the
noise/jitter PLL. The
from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms.
OUT
AD9739
/f
CLK
) when the DAC clock path contribution, along with
can be used to square-up the signal and provide a
ADCLK914
clock receiver provides optimum jitter performance
ADF4350
FREF
driven by a high quality RF signal
AD9739
50Ω
can provide output frequencies
50Ω
clock receiver. Note that all
PLL
10nF
10nF
ADF4350
ADF4350
Figure 59.
D
D
V
V
Figure 60.
VCO
REF
T
50Ω
low phase
ADCLK914
DIV-BY-2
ADF4350
N = 0 – 4
50Ω
Rev. B | Page 39 of 48
N
V
V
Interface to the
CC
EE
Interface to the
V
VCO
ADCLK914
RF
RF
RF
RF
Each single-ended output can provide a squared-up output level
that can be varied from −4 dBm to +5 dBm allowing for >2 V p-p
output differential swings. The
additional CML buffer that can be used to drive another
AD9739
The
adjust the common-mode level of its inputs over a span of
±100 mV centered about its midsupply point (that is, VDDC/2)
as well as an offset for hysteresis purposes. Figure 58 shows the
equivalent input circuit of one of the inputs. ESD diodes are not
shown for clarity purposes. It has been found through
characterization that the optimum setting is for both inputs to
be biased at approximately 0.8 V. This can be achieved by writing a
0x0F (corresponding to a −15) setting to both cross controller
registers (that is, Register 0x22 and Register 0x23).
OUT
OUT
OUT
OUT
AD9739
AD9739
A+
A–
A+
A–
AD9739
Q
Q
DACCLK_N
DACCLK_P
device.
CLK Input
CLK Input
1.8V p-p
Figure 58. Clock Input and Common-Mode Control
50Ω
clock receiver features the ability to independently
50Ω
3.9nH
1nF
1nF
100Ω
1nF
1nF
100Ω
ESD
IOUT ARRAY
IOUT ARRAY
AD9739
4-BIT NMOS
4-BIT PMOS
CLKx_OFFSET
CLKx_OFFSET
DACCLK_P
DACCLK_N
DACCLK_P
DACCLK_N
AD9739
DIR_x = 0
DIR_x = 0
ADF4350
also includes an
VDDC
VSSC
AD9739