AD9739 Analog Devices, AD9739 Datasheet - Page 3

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
Deleted DOCSIS Performance Section and
Figure 46 to Figure 72 .....................................................................19
Added Figure 35 through Figure 38; Renumbered Sequentially....19
Changes to SPI Register Map Section and Table 9......................20
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC® Section, Controller
Clock Disable Section, Interrupt Request (IRQ) Enable/Status
Section, and Table 10 to Table 13 ..................................................22
Added TxDAC Full-Scale Current Setting (I
Section, TxDAC Quad-Switch Mode of Operation Section, DCI
Phase Alignment Status Section, SYNC_IN Phase Alignment
Status Section, Data Receiver Controller Configuration Section,
and Table 14 to Table 18 .................................................................23
Added Data Receiver Controller_Data Sample Delay Value
Section, Data and Sync Receiver Controller_DCI Delay
Value/Window and Phase Rotation Section, Data Receiver
Controller_Delay Line Status and Sync Controller SYNC_OUT
Status Section, and Table 19 to Table 21.......................................24
Deleted Serial Peripheral Interface Section, General Operation
of the Serial Interface Section, Instruction Mode (8-Bit Instruction)
Section, and Serial Interface Port Pin Description Section .......25
Added Sync and Data Receiver Controller Lock/Tracking Status
Section, CLK Input Common Mode Section, Mu Controller
Configuration and Status Section, and Table 22 to Table 24.....25
Deleted MSB/LSB Transfers Section, Serial Port Configuration
Section, and Figure 74 to Figure 79 ..............................................26
Added Part ID Section and Table 25 ............................................26
Changes to Theory of Operation Section ....................................27
Added Figure 39 ..............................................................................27
Deleted SPI Registers Section and Table 8 to Table 31...............28
Moved and Changes to LVDS Data Port Interface Section .......28
Added Figure 40 and Figure 41 .....................................................28
Changes to Figure 42 ......................................................................29
Moved and Changes to Figure 43..................................................29
Added Data Receiver Controller Initialization Description
Section, Table 26, and Data Receiver Operation at Lower Clock
Rates Section ....................................................................................30
Added LVDS Driver and Receiver Input Section, Figure 44 to
Figure 47, and Table 27...................................................................31
Changed and Moved Mu Delay Controller Section to Mu
Controller Section ...........................................................................32
Changes to Mu Controller Section, Figure 48, and Figure 49...32
Added Figure 50 and Table 28 .......................................................32
Added Mu Controller Initialization Description Section..........33
Changes to Interrupt Requests Section ........................................34
Added Table 29 ................................................................................34
Changed Synchronization Controller Section to Multiple
Device Synchronization Section....................................................35
Added Figure 52 ..............................................................................35
Changes to Figure 53 ......................................................................36
Added Sync Controller Initialization Description Section........36
Added Synchronization Limitations Section...............................37
Changed Applications Information to Analog Interface
Considerations Section...................................................................38
OUTFS
) and Sleep
Rev. B | Page 3 of 48
Changes to Analog Modes of Operation Section .......................38
Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39
Added Clock Input Considerations Section, Figure 58 to
Figure 60...........................................................................................39
Deleted Clock Phase Noise Affects on AC Performance Section,
Table 32 to Table 34, Applying Data to the AD9739 Section, and
Figure 87...........................................................................................40
Moved Figure 61..............................................................................40
Changes to Voltage References Section and Analog Outputs
Section ..............................................................................................40
Added Equivalent DAC Output and Transfer Function and
Figure 63...........................................................................................40
Deleted Mu Control Operation Section, Search Mode Section,
and Figure 89 ...................................................................................41
Moved Figure 64..............................................................................41
Added Peak DAC Output Power Capability Section and Figure 65. 41
Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay
and Phase Readback Section, Operating the Mu Controller
Manually Section, and Calculating Mu Delay Line Step Size
Section ..............................................................................................42
Added Output Stage Configuration Section and Figure 66 to
Figure 70...........................................................................................42
Added Nonideal Spectral Artifacts Section, Figure 71, and
Table 30.............................................................................................43
Deleted Operation in Master Mode, Figure 93, and
Figure 94...........................................................................................44
Added Lab Evaluation of the AD9739 Section, Power Dissipation
and Supply Domains Section, and Figure 72 to Figure 74.........44
Deleted Figure 95, Operation in Slave Mode Section, and Data
Receiver Operation in Auto Mode Section..................................45
Changes to Recommended Start-Up Sequence Section ............45
Added Figure 75 ..............................................................................45
Deleted Figure 97, Data Receiver Operation in Manual Mode
Section, Calculating the DCI Delay Line Step Size Section, and
Maximum Allowable Data Timing Skew/Jitter Section.............46
Added Table 31 ................................................................................46
Deleted Optimizing the Clock Common-Mode Voltage Section,
Figure 99, Analog Control Registers Section, Mirror Roll-Off
Frequency Control Section, and Figure 101................................47
Added Table 32 ................................................................................47
Deleted Figure 103, Figure 104, and Figure 106 .........................48
Updated Outline Dimensions........................................................48
Deleted Figure 107 to Figure 109 ..................................................49
Deleted Table 35 to Table 44 ..........................................................50
7/11—Rev 0 to Rev A
Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,
DACCLK_N), Added DAC Clock Rate .........................................4
Changes to Table 3, Added Dynamic Performance Parameters.......5
Change to Ordering Guide ............................................................53
2/09—Revision 0: Initial Release
AD9739