AD9739A Analog Devices, AD9739A Datasheet - Page 50

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9737A/AD9739A
The DIV-BY-4 circuit generates four clock phases that serve as
inputs to the data receiver controller. All DDR registers in the
data and DCI paths operate on both clock edges; however, for
clarity purposes, only the phases (that is, 0° and 90°) corresponding
to the positive edge of each path are shown. One of the DIV-BY-
4 phases is used to generate the DCO signal; therefore, the phase
relationship between DCO and clocks fed into the controller
remains fixed. Note that it is this attribute that allows possible
factory calibration of images and clock spurs that are attributed
to f
After this data has been successively sampled into the first set of
registers, an elastic FIFO is used to transfer the data into the
AD9737A/AD9739A
continuously between the two clock domains, the data receiver
controller should always be enabled and placed into track mode
(Register 0x10, Bit 1 and Bit 0). Tracking mode operates cont-
inuously in the background to track delay variations between
the host and
ensuring that the DCI signal is sampled within a very narrow
window defined by two internally generated clocks (that is, PRE
and PST), as shown in Figure 161. Note that proper sampling of
the DCI signal can also be confirmed by monitoring the status
of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0
(Register 0x0C, Bit 0). If the delay settings are correct, the state
of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0
should be 1.
DAC
FINE DELAY
FINE DELAY
/4 modulation of the critical DAC clock.
Figure 161. Pre- and Post-Delay Sampling Diagram
PRE
PST
DCI
DBx[13:1]
AD9737A/AD9739A
DCO
DCI
clock domain. To track any phase variation
FINE_DEL_SKEW
DDR
DDR
DDR
DDR
FF
FF
FF
FF
DCI WINDOW POST
DCI WINDOW PRE
DCI WINDOW SAMPLE
clock domains. It does so by
SAMPLE
DELAY
DELAY
DELAY
POST
FINE
PRE
FINE
FINE
Figure 160. Top Level Diagram of the Data Receiver Controller
DATA RECEIVER CONTROLLER
ELASTIC FIFO
DDR
FF
DELAY
DELAY
Rev. | Page 50 of 64
C
DDR
FF
STATE MACHINE/
TRACKING LOOP
DCI DELAY
The skew or window width (FINE_DEL_SKEW) is set via
Register 0x13, Bits[3:0], with a maximum skew of approximately
300 ps and resolution of 12 ps. It is recommended that the skew
be set to 36 ps (that is, Register 0x13 = 0x72) during initialization.
Note that the skew setting also affects the speed of the controller
loop, with tighter skew settings corresponding to longer
response time.
Data Receiver Controller Initialization Description
The data controller should be initialized and placed into track
mode as the second step in the SPI boot sequence. The following
steps are recommended for the initialization of the data receiver
controller:
1.
2.
3.
4.
5.
6.
SAMPLE
DELAY
DELAY
DELAY
Set FINE_DEL_SKEW to 2 for a larger DCI sampling window
(Register 0x13 = 0x72). Note that the default DCI_DEL and
SMP_DEL settings of 167 are optimum.
Disable the controller before enabling (that is, Register 0x10
= 0x00).
Enable the Rx controller in two steps: Register 0x10 = 0x02
followed by Register 0x10 = 0x03.
Wait 135 k clock cycles.
Read back Register 0x21 and confirm that it is equal to
0x05 to ensure that the DLL loop is locked and tracking.
Read back the DCI_DEL value to determine whether the
value falls within a user defined tracking guard band. If it
does not, go back to Step 2.
SAMPLE
DELAY
DDR
DELAY
PATH
FF
PATH
DCI
DATA TO
CORE
180
270
0
90
DIV-BY-4
F
DAC
Data Sheet