AD9739A Analog Devices, AD9739A Datasheet - Page 40

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9737A/AD9739A
SERIAL PORT INTERFACE (SPI) REGISTER
SPI REGISTER MAP DESCRIPTION
The
described in Table 10, that are used to configure and monitor
various internal parameters. Note the following points when
programming the
•
•
•
•
•
Reset
Issuing a hardware or software reset places the AD9737A/
AD9739A
(excluding 0x00) are set to their default states, as described in
Table 10, upon issuing a reset. After issuing a reset, the SPI
initialization process needs only to write to registers that are
required for the boot process as well as any other register
settings that must be modified, depending on the target
application.
Although the
power-on reset (POR), it is still recommended that a software
or hardware reset be implemented shortly after power-up. The
internal reset signal is derived from a logical OR operation from
the internal POR signal, the RESET pin, and the software reset
state. A software reset can be issued via the reset bit (Register 0x00,
Bit 5) by toggling the bit high, then low. Note that, because the
MSB/LSB format may still be unknown upon initial power-up
(that is, internal POR is unsuccessful), it is also recommended
that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for
the instruction cycle that issues a software reset. A hardware
reset can be issued from a host or external supervisory IC by
applying a high pulse with a minimum width of 40 ns to the RESET
pin (that is, Pin F14). RESET should be tied to VSS if unused.
Table 9. SPI Registers Pertaining to SPI Options
Address (Hex)
0x00
AD9737A/AD9739A
Registers pertaining to similar functions are grouped together
and assigned adjacent addresses.
Bits that are undefined within a register should be assigned
a 0 when writing to that register.
Registers that are undefined should not be written to.
A hardware or software reset is recommended on power-
up to place SPI registers in a known state.
A SPI initialization routine is required as part of the boot
process. See Table 29 for an example procedure.
SPI registers in a known state. All SPI registers
AD9737A/AD9739A
AD9737A/AD9739A
Bit
7
6
5
contain a set of programmable registers,
Description
Enable 3-wire SPI
Enable SPI LSB first
Software reset
do feature an internal
SPI registers:
Rev. | Page 40 of 64
C
SPI OPERATION
The serial port of the
has a 3- or 4-wire SPI capability, allowing read/write access
to all registers that configure the device’s internal parameters.
It provides a flexible, synchronous serial communications
port, allowing easy interface to many industry-standard
microcontrollers and microprocessors. The 3.3 V serial I/O is
compatible with most synchronous transfer formats, including
the Motorola® SPI and the Intel® SSR protocols.
The default 4-wire SPI interface consists of a clock (SCLK),
serial port enable ( CS ), serial data input (SDIO), and serial data
output (SDO). The inputs to SCLK, CS , and SDIO contain a
Schmitt trigger with a nominal hysteresis of 0.4 V centered about
VDD33/2. The maximum frequency for SCLK is 20 MHz. The
SDO pin is active only during the transmission of data and
remains three-stated at any other time.
A 3-wire SPI interface can be enabled by setting the SDIO_DIR
bit (Register 0x00, Bit 7). This causes the SDIO pin to become
bidirectional such that output data appears on only the SDIO
pin during a read operation. The SDO pin remains three-stated
in a 3-wire SPI interface.
Instruction Header Information
MSB
17
R/W
An 8-bit instruction header must accompany each read and write
operation. The MSB is a R/ W indicator bit with logic high
indicating a read operation. The remaining seven bits specify
the address bits to be accessed during the data transfer portion.
The eight data bits immediately follow the instruction header
for both read and write operations. For write operations, registers
change immediately upon writing to the last bit of each transfer
byte. CS can be raised after each sequence of eight bits (except
the last byte) to stall the bus. The serial transfer resumes
when CS is lowered. Stalling on nonbyte boundaries resets the SPI.
16
A6
SCLK (PIN H13)
SDIO (PIN G14)
SDO (PIN H14)
CS
Figure 152.
(PIN G13)
15
A5
AD9737A/AD9739A,
AD9737A/AD9739A
14
A4
AD9737A/AD9739A
13
A3
SPI PORT
SPI Port
shown in Figure 152,
12
A2
Data Sheet
LSB
11
A1
10
A0