AD9739A Analog Devices, AD9739A Datasheet - Page 3

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
REVISION HISTORY
2/12—Rev. B to Rev. C
Changes to Figure 5 ........................................................................... 9
Changes to Table 7 .......................................................................... 11
Changes to Ordering Guide ........................................................... 63
2/12—Rev. A to Rev. B
Added AD9737A ................................................................ Universal
Reorganized Layout ........................................................... Universal
Moved Revision History Section ..................................................... 3
Deleted ±6% from Table Summary Statement; Changes
to Table 1 ............................................................................................ 4
Deleted ±6% from Table Summary Statement, Table 2 ................ 5
Deleted ±6% from Table Summary Statement, Table 3 ................ 6
Changes to AC Specifications Section and Table 4 ....................... 7
Added Figure 5, Renumbered Sequentially ................................... 9
Added Figure 7 and Table 7, Renumbered Sequentially ............ 10
Deleted Figure 24 ............................................................................ 13
Added Typical Performance Characteristics—AD9737A
Section and Figure 9 to Figure 77 ................................................. 14
Deleted Table 9 ................................................................................ 25
Added Static Linearity Section and Figure 78 to Figure 88 ............ 26
Added Figure 106 ............................................................................ 30
Changes to Figure 116, Figure 117, Figure 118, Figure 119,
Figure 120, and Figure 121 ............................................................. 33
Changes to Figure 122, Figure 123, Figure 124, Figure 125,
Figure 126, and Figure 127 ............................................................. 34
Changes to Figure 128, Figure 129, Figure 130, Figure 131,
Figure 132, and Figure 133 ............................................................. 35
Changes to Figure 134, Figure 135, Figure 136, Figure 137,
Figure 138, and Figure 139 ............................................................. 36
Changes to Figure 140, Figure 141, Figure 142, Figure 143,
Figure 144, and Figure 145 ............................................................. 37
Changes to Figure 146, Figure 147, Figure 148, Figure 149,
and Figure 150; Added Figure 151 ................................................ 38
Added Table 10 ................................................................................ 42
Rev. C | Page 3 of 64
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................ 43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC
Full-Scale Current Setting (I
Quad-Switch Mode of Operation Section, DCI Phase
Alignment Status Section, Data Receiver Controller
Configuration Section, and Table 14 to Table 18 ........................ 44
Added Data Receiver Controller_Data Sample Delay Value
Section, Data Receiver Controller_DCI Delay Value/Window
and Phase Rotation Section, Data Receiver Controller_Delay
Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ...................................... 45
Added CLK Input Common Mode Section, and Mu
Controller Configuration and Status Section, and Table 23
and Table 24 ..................................................................................... 46
Added Part ID Section, and Table 25 ........................................... 47
Changes to LVDS Data Port Interface Section ............................ 49
Changes to Data Receiver Controller Initialization
Description Section ........................................................................ 51
Changes to Mu Controller Section ............................................... 52
Added Figure 167 and Table 27, Changes to Mu Controller
Initialization Description Section ................................................. 53
Changes to Analog Modes of Operation Section, Figure 171,
and Figure 172 ................................................................................. 55
Updated Outline Dimensions ........................................................ 63
Changes to Ordering Guide ........................................................... 63
7/11—Rev. 0 to Rev. A
Changed Maximum Update Rate (DACCLK Input) Parameter
to DAC Clock Rate Parameter in Table 4 ....................................... 6
Added Adjusted DAC Update Rate Parameter and Endnote 1 in
Table 4 ................................................................................................. 6
Updated Outline Dimensions ........................................................ 43
1/11—Revision 0: Initial Version
OUTFS
) and Sleep Section, TxDAC
AD9737A/AD9739A