AD9739A Analog Devices, AD9739A Datasheet - Page 41

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
The
significant bit (MSB) first and least significant bit (LSB) first
data formats. Figure 153 illustrates how the serial port words
are formed for the MSB first and LSB first modes. The bit order
is controlled by the LSB/MSB bit (Register 0x00, Bit 6). The
default value of Bit 6 is 0, MSB first. When the LSB/MSB bit is
set high, the serial port interprets both instruction and data bytes
LSB first.
SDATA
SDATA
SCLK
SCLK
CS
CS
AD9737A/AD9739A
Figure 153. SPI Timing, MSB First (Upper) and LSB First (Lower)
R/W
A0
N1
A1 A2
INSTRUCTION CYCLE
INSTRUCTION CYCLE
N2
A4
A3
A3 A2
A4
N2
serial port can support both most
A1
N1
R/W
A0
SCLK
SCLK
SDO
SCLK
SDIO
SDIO
SDIO
CS
CS
D7
D0
CS
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
1
1
D6
D1
1
1
t
t
t
DS
DS
DS
Figure 155. SPI 3-Wire Read Operation Timing
t
Figure 156. SPI 4-Wire Read Operation Timing
t
t
t
t
t
HI
S
S
HI
HI
S
D6
D1
1/
1/
1/
Figure 154. SPI Write Operation Timing
R/W
R/W
R/W
t
N
N
f
t
f
t
f
DH
DH
SCLK
SCLK
SCLK
DH
D7
D0
N
N
N1
N1
t
t
t
LOW
LOW
LOW
N1
Rev. | Page 41 of 64
A2
A2
C
N0
A1
A1
A0
A0
A0
Figure 154 illustrates the timing requirements for a write
operation to the SPI port. After the serial port enable ( CS )
signal goes low, data (SDIO) pertaining to the instruction
header is read on the rising edges of the clock (SCLK). To
initiate a write operation, the read/not-write bit is set low. After
the instruction header is read, the eight data bits pertaining to
the specified register are shifted into the SDIO pin on the rising
edge of the next eight clock cycles.
Figure 155 illustrates the timing for a 3-wire read operation to
the SPI port. After CS goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high. After
the address bits of the instruction header are read, the eight data
bits pertaining to the specified register are shifted out of the
SDIO pin on the falling edges of the next eight clock cycles.
Figure 156 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin only, whereas
the SDIO pin remains at high impedance throughout the
operation. The SDO pin is an active output only during the data
transfer phase and remains three-stated at all other times.
t
t
DV
DV
D7
D7
D7
D6
D6
D6
D1
D1
D1
D0
D0
t
H
D0
t
t
t
EZ
EZ
EZ
AD9737A/AD9739A