AD9739A Analog Devices, AD9739A Datasheet - Page 48

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9737A/AD9739A
THEORY OF OPERATION
The
with a specified update rate of 1.6 GSPS to 2.5 GSPS. Figure 157
shows a top-level functional diagram of the AD9737A/AD9739A.
A high performance TxDAC core delivers a signal dependent,
differential current (nominal ±10 mA) to a balanced load
referenced to ground. The frequency of the clock signal appearing
at the
sets the TxDAC’s update rate. This clock signal, which serves as
the master clock, is routed directly to the TxDAC as well as to a
clock distribution block that generates all critical internal and
external clocks.
The
and DB1) to reduce the data interface rate to ½ the TxDAC
update rate. The host processor drives deinterleaved data with
offset binary format onto the DB0 and DB1 ports, along with
an embedded DCI clock that is synchronous with the data.
Because the interface is double data rate (DDR), the DCI clock
is essentially an alternating 0-1 bit pattern with a frequency that
is equal to ¼ the TxDAC update rate (f
ronization with the host processor, the
passes an LVDS clock output (DCO) that is also equal to the
DCI frequency.
The
internal sampling clock for the DDR receiver such that the data
instance sampling is optimized. When enabled and configured
properly for track mode, it ensures proper data recovery between
the host and the
receiver controller has the ability to track several hundreds of
picoseconds of drift between these clock domains, typically caused
by supply and temperature variation.
As mentioned, the host processor provides the AD9737A/
AD9739A
and DB1 data ports receive alternating samples (that is, odd/even
data streams). The
to reassemble (that is, multiplex) the odd/even data streams
into their original order before delivery into the TxDAC for
signal reconstruction. The pipeline delay from a sample being
latched into the data port to when it appears at the DAC output
is on the order of 78 (±) DACCLK cycles.
AD9739A
AD9737A/AD9739A
AD9737A/AD9739A
AD9737A/AD9739A
with a deinterleaved data stream such that the DB0
and the
AD9737A/AD9739A
AD9737A/AD9739A
AD9737A
include two LVDS data ports (DB0
data receiver controller generates an
differential clock receiver, DACCLK,
are 14- and 11-bit TxDACs
clock domains. The data
DAC
AD9737A/AD9739A
data assembler is used
). To simplify synch-
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C
The
circuit controlled via a Mu controller to optimize the timing
hand-off between the
and TxDAC core. Besides ensuring proper data reconstruction,
the TxDAC’s ac performance is also dependent on this critical
hand-off between these clock domains with speeds of up to
2.5 GSPS. Once properly initialized and configured for track
mode, the DLL maintains optimum timing alignment over
temperature, time, and power supply variation.
A SPI interface is used to configure the various functional blocks
as well as monitor their status for debug purposes. Proper
operation of the
blocks be initialized upon power-up. A simple SPI initialization
routine is used to configure the controller blocks (see Table 28).
An IRQ output signal is available to alert the host should any of
the controllers fall out of lock during normal operation.
The following sections discuss the various functional blocks
in more detail as well as their implications when interfacing
to external ICs and circuitry. Although a detailed description of
the various controllers (and associated SPI registers used to
configure and monitor) is also included for completeness, the
recommended SPI boot procedure can be used to ensure
reliable operation.
SCLK
SDIO
SDO
DCO
CS
DCI
AD9737A/AD9739A
Figure 157. Functional Block Diagram of the
RESET
SPI
CLK DISTRIBUTION
AD9737A/AD9739A
(DIV-BY-4)
AD9737A/AD9739A
includes a delay lock loop (DLL)
IRQ
AD9737A/AD9739A
DAC BIAS
(MU CONTROLLER)
requires that controller
DACCLK
TxDAC
CORE
AD9737A/AD9739A
DLL
digital clock domain
Data Sheet
1.2V
VREF
I120
IOUTN
IOUTP