AD6672 Analog Devices, AD6672 Datasheet - Page 9

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
t
t
t
t
t
t
t
t
t
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
Test Conditions/Comments
See Figure 42 for the SPI timing diagram
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 42)
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 42)
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Min
2
2
40
2
2
10
10
10
10
Typ
Max
AD6672
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns