AD6672 Analog Devices, AD6672 Datasheet - Page 18

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6672
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6672.
The full-scale input range can be adjusted by varying the
reference voltage via SPI. The input span of the ADC tracks
reference voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased
internally (see Figure 29) and require no external bias. If the
inputs are floated, the CLK− pin is pulled low to prevent
spurious clocking.
Clock Input Options
The
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 30 and Figure 31 show two preferable methods for
clocking the
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 250 MHz. The
back-to-back Schottky diodes across the secondary winding of
the transformer limit clock excursions into the
approximately 0.8 V p-p differential. This limit helps prevent
the large voltage swings of the clock from feeding through to
other portions of the
fall times of the signal, which are critical for low jitter
performance.
CLOCK
INPUT
Figure 30. Transformer-Coupled Differential Clock (Up to 250 MHz)
AD6672
CLK+
Figure 29. Simplified Equivalent Clock Input Circuit
50Ω
390pF
AD6672
has a very flexible clock input structure. Clock
100Ω
4pF
ADT1-1WT, 1:1Z
Mini-Circuits
AD6672
(at clock rates of up to 625 MHz). A low
XFMR
AVDD
0.9V
while preserving the fast rise and
®
390pF
390pF
AD6672
SCHOTTKY
HSMS2822
DIODES:
sample clock inputs,
AD6672
4pF
CLK+
CLK–
CLK–
ADC
to
Rev. 0 | Page 18 of 32
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 32. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and
ADCLK925
CLOCK
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 33. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516,
AD9517, AD9518, AD9520, AD9522, AD9523, and
clock drivers offer excellent jitter performance.
CLOCK
CLOCK
Input Clock Divider
The
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1, the duty cycle stabilizer (DCS) is
enabled by default on power-up.
INPUT
INPUT
INPUT
INPUT
CLOCK
AD6672
INPUT
50kΩ
50kΩ
Figure 31. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 33. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 32. Differential PECL Sample Clock (Up to 625 MHz)
390pF
clock drivers offer excellent jitter performance.
contains an input clock divider with the ability to
1nF
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
50kΩ
AD95xx,
ADCLK9xx
PECL DRIVER
AD95xx
LVDS DRIVER
25Ω
25Ω
240Ω
390pF
390pF
ADCLK905/ADCLK907/
SCHOTTKY
HSMS2822
DIODES:
240Ω
0.1µF
0.1µF
100Ω
0.1µF
0.1µF
100Ω
CLK+
CLK–
ADC
AD9524
CLK+
CLK–
CLK+
CLK–
ADC
ADC