AD6672 Analog Devices, AD6672 Datasheet - Page 7

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUTS (SDIO)
DIGITAL OUTPUTS (OR+, OR−)
1
2
Pull-up.
Pull-down.
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LVDS Data and OR Outputs
Differential Output Voltage (V
Output Offset Voltage (V
Differential Output Voltage (V
Output Offset Voltage (V
1
2
1
OS
OS
), ANSI Mode
), Reduced Swing Mode
OD
OD
), ANSI Mode
), Reduced Swing Mode
Rev. 0 | Page 7 of 32
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
0.3
AGND
0.9
10
−22
12
1.22
0
50
−5
1.22
0
45
−5
1.22
0
45
−5
250
1.15
150
1.15
CMOS/LVDS/LVPECL
Typ
0.9
4
15
26
2
26
2
26
5
350
1.25
200
1.25
Max
3.6
AVDD
1.4
+22
−10
18
2.1
0.6
71
+5
2.1
0.6
70
+5
2.1
0.6
70
+5
450
1.35
280
1.35
AD6672
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
mV
V
mV
V