AD6672 Analog Devices, AD6672 Datasheet - Page 20

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6672
DIGITAL OUTPUTS
The
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
As detailed in the
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The
output pins. The three-state mode is enabled using the SPI
interface. The data outputs can be three-stated by using the
output enable bar bit (Bit 4) in Register 0x14. This OEB
function is not intended for rapid access to the data bus.
Timing
The
10 input sample clock cycles when NSR is disabled and provides
13 input sample clock cycles when NSR is enabled. Data outputs
Table 10. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AD6672
AD6672
AD6672
output drivers can be configured for either ANSI
has a flexible three-state ability for the digital
provides latched data with a pipeline delay of
AN-877 Application
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
<−0.875
−0.875
0
+0.875
>+0.875
Note, Interfacing to High
Offset Binary Output Mode
000 0000 0000
100 0000 0000
111 1111 1111
000 0000 0000
111 1111 1111
Rev. 0 | Page 20 of 32
are available one propagation delay (t
the clock signal.
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD6672.
These transients may degrade converter dynamic performance.
The lowest typical conversion rate of the
clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The
intended for capturing the data in an external register. Figure 2
shows a timing diagram of the
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
AD6672
also provides the data clock output (DCO)
Twos Complement Mode (Default)
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
AD6672
PD
) after the rising edge of
AD6672
output modes.
is 40 MSPS. At
OR
1
0
0
0
1