AD6672 Analog Devices, AD6672 Datasheet - Page 11

• Manufacturer Part Number: AD6672
• Description: IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6672

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
ADC Analog
Digital Outputs
SPI Control
8, 17
3, 27, 28, 31, 32
0
25
30
29
26
1
2
5
4
7
6
10
9
12
11
14
13
16
15
19
18
21
20
23
22
24
Mnemonic
DRVDD
AGND,
Exposed Paddle
DNC
VIN+
VIN−
VCM
CLK+
CLK−
OR+
OR−
0/D0+ (LSB)
0/D0− (LSB)
D1+/D2+
D1−/D2−
D3+/D4+
D3−/D4−
D5+/D6+
D5−/D6−
D7+/D8+
D7−/D8−
D9+/D10+ (MSB)
D9−/D10− (MSB)
DCO+
DCO−
SCLK
SDIO
CSB
AVDD
Type
Supply
Supply
Ground
Input
Input
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/output
Input
NOTES
1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
2. DNC = NO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
0/D0– (LSB)
0/D0+ (LSB)
PACKAGE PROVIDES THE ANALOG GROUND FOR THE
PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
DRVDD
AVDD
CLK+
CLK–
OR–
OR+
Figure 3. LFCSP Pin Configuration (Top View)
1
2
3
4
5
6
7
8
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal paddle on the bottom of the package provides the
analog ground for the part. This exposed paddle must be connected to ground for proper
operation.
Do Not Connect. Do not connect to this pin.
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to
ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Overrange indicator—True.
Overrange indicator—Complement.
DDR LVDS Output Data 0—True. The output bit on the rising edge of the data clock output
(DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 0—Complement. The output bit on the rising edge of the data clock
output (DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 1/2—True.
DDR LVDS Output Data 1/2—Complement.
DDR LVDS Output Data 3/4—True.
DDR LVDS Output Data 3/4—Complement.
DDR LVDS Output Data 5/6—True.
DDR LVDS Output Data 5/6—Complement.
DDR LVDS Output Data 7/8—True.
DDR LVDS Output Data 7/8—Complement.
DDR LVDS Output Data 9/10—True.
DDR LVDS Output Data 9/10—Complement.
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
INTERLEAVED
Rev. 0 | Page 11 of 32
(Not to Scale)
AD6672
TOP VIEW
LVDS
24 CSB
23 SCLK
22 SDIO
21 DCO+
20 DCO–
19 D9+/D10+ (MSB)
18 D9–/D10– (MSB)
17 DRVDD
AD6672