SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 889

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

Figure 35-10. Method 1 (UPDM = 0)
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Method 1: Manual write of duty-cycle values and manual trigger of the update
UPDULOCK
CDTYUPD
CCNT0
CDTY
0x20
0x20
In this mode, the update of the period value, the duty-cycle values and the dead-time values
must be done by writing in their respective update registers with the CPU (respectively
PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK of the
Update Control Register”
PWM period) the synchronous channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read
0.
Sequence for Method 1:
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
1. Select the manual write of duty-cycle values and the manual update by setting the
2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time val-
5. Set UPDULOCK to 1 in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this
synchronous channels.
UPDM field to 0 in the PWM_SCM register
ues is required, write registers that need to be updated (PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPDx).
moment the UPDULOCK bit is reset, go to
0x40
0x40
0x60
(PWM_SCUC) which allows to update synchronously (at the same
0x60
Step
4.) for new values.
SAM3S8/SD8
SAM3S8/SD8
“PWM Sync Channels
889
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