SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 796

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

Figure 33-20. 2-bit Gray Up/Down Counter.
33.6.16
33.6.17
796
796
TIOAx
TIOBx
DOWNx
SAM3S8/SD8
SAM3S8/SD8
Write Protection System
Fault Mode
TC_RCx
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx,
TC_RAx, TC_RBx, TC_RCx registers. When this mode is enabled and one of the protected reg-
isters write, the register write request canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires the use of a security code. Thus when enabling or disabling the write protection
mode the WPKEY field of the TC_WPMR register must be filled with the “TIM” ASCII code (cor-
responding to 0x54494D) otherwise the register write will be canceled.
At anytime, the TC_RCx registers can be used to perform a comparison on the respective cur-
rent channel counter value (TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the
required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 register
and/or CPCS from TC_SR1 register. Each source can be independently enabled/disabled by
means of TC_FMR register.
This can be useful to detect an overflow on speed and/or position when QDEC is processed and
to act immediately by using the FAULT output.
Figure 33-21. Fault Output Generation
TC_SR0 flag CPCS
TC_SR1 flag CPCS
TC_FMR / ENCF0
TC_FMR / ENCF1
WAVEx = GCENx =1
AND
AND
OR
FAULT (to PWM input)
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12