SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 76

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

76
76
SAM3S8/SD8
SAM3S8/SD8
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic
ISB
IT
LDM
LDMDB,
LDMEA
LDMFD,
LDMIA
LDR
LDRB,
LDRBT
LDRD
LDREX
LDREXB
LDREXH
LDRH,
LDRHT
LDRSB,
LDRSBT
LDRSH,
LDRSHT
LDRT
LSL, LSLS
LSR, LSRS
MLA
MLS
MOV, MOVS
MOVT
MOVW, MOV
MRS
MSR
MUL, MULS
MVN, MVNS
NOP
ORN, ORNS
ORR, ORRS
POP
PUSH
Operands
-
-
Rn{!}, reglist
Rn{!}, reglist
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn]
Rt, [Rn]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rd, Rm, <Rs|#n>
Rd, Rm, <Rs|#n>
Rd, Rn, Rm, Ra
Rd, Rn, Rm, Ra
Rd, Op2
Rd, #imm16
Rd, #imm16
Rd, spec_reg
spec_reg, Rm
{Rd,} Rn, Rm
Rd, Op2
-
{Rd,} Rn, Op2
{Rd,} Rn, Op2
reglist
reglist
Brief description
Instruction Synchronization Barrier
If-Then condition block
Load Multiple registers, increment after -
Load Multiple registers, decrement
before
Load Multiple registers, increment after -
Load Register with word
Load Register with byte
Load Register with two bytes
Load Register Exclusive
Load Register Exclusive with byte
Load Register Exclusive with halfword
Load Register with halfword
Load Register with signed byte
Load Register with signed halfword
Load Register with word
Logical Shift Left
Logical Shift Right
Multiply with Accumulate, 32-bit result
Multiply and Subtract, 32-bit result
Move
Move Top
Move 16-bit constant
Move from special register to general
register
Move from general register to special
register
Multiply, 32-bit result
Move NOT
No Operation
Logical OR NOT
Logical OR
Pop registers from stack
Push registers onto stack
Flags
-
-
-
-
-
-
-
-
-
-
-
-
N,Z,C
N,Z,C
-
-
N,Z,C
-
-
N,Z,C,V
N,Z
N,Z,C
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
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