SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 167

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

10.20.4
• PENDSVSET
RW
PendSV set-pending bit.
Write:
0 = no effect
1 = changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
• PENDSVCLR
WO
PendSV clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the PendSV exception.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Reserved for
Reserved
Debug
31
23
15
7
Interrupt Control and State Register
ISRPENDING
30
22
14
6
VECTPENDING
Reserved
The ICSR:
See the register summary in
on page
• provides:
• indicates:
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
– whether any interrupts are pending.
191, for the ICSR attributes. The bit assignments are:
29
21
13
5
PENDSVSET
28
20
12
4
VECTACTIVE
Table 10-30 on page
PENDSVCLR
RETTOBASE
27
19
11
3
VECTPENDING
164, and the Type descriptions in
PENDSTSET
26
18
10
2
Reserved
PENDSTCLR
SAM3S8/SD8
SAM3S8/SD8
25
17
9
1
VECTACTIVE
Table 10-33
Reserved
24
16
8
0
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