ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 37

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

9.12
9.12.1
9.12.2
9223B–AVR–09/11
Register Description
OSCCAL – Oscillator Calibration Register
CLKPR – Clock Prescale Register
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value
is automatically written to this register during chip reset, giving the Factory calibrated fre-
quency as specified in
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as
specified in
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6...0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in
the range.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written.
Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period,
nor clear the CLKPCE bit.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced when a division factor is used. The division factors are given
in
Bit
(0x66)
Read/Write
Initial Value
Bit
(0x61)
Read/Write
Initial Value
Table 9-17 on page
Atmel ATmega48PA/88PA/168PA [Preliminary]
Table 29-3 on page
CLKPCE
CAL7
R/W
R/W
7
7
0
38.
CAL6
Table 29-3 on page
R/W
6
R
6
–
0
317. Calibration outside that range is not guaranteed.
CAL5
R/W
5
R
5
0
–
Device Specific Calibration Value
CAL4
R/W
4
R
4
–
0
317. The application software can write this
CLKPS3
CAL3
R/W
R/W
3
3
CLKPS2
See Bit Description
CAL2
R/W
R/W
2
2
CLKPS1
CAL1
R/W
R/W
1
1
CLKPS0
CAL0
R/W
R/W
0
0
OSCCAL
CLKPR
37