ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 285

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

27.8.6
27.8.7
27.8.8
27.8.9
9223B–AVR–09/11
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the
BLS as described in
addressing the RWW section after the programming is completed, the user software must
clear the RWWSB by writing the RWWSRE. See
Loader” on page 288
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
See
Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SELFPRGEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended
to load the Z-pointer with 0x0001 (same as used for reading the lO
bility it is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When
programming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading
the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user checks the status bit (EEPE) in the EECR Register and
verifies that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are
set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLB-
SET and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no
LPM instruction is executed within three CPU cycles or no SPM instruction is executed within
four CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in
the Instruction set Manual.
Bit
R0
Bit
Rd
Atmel ATmega48PA/88PA/168PA [Preliminary]
Table 27-2
and
7
1
7
–
Table 27-3
“Watchdog Timer” on page
for an example.
6
1
6
–
for how the different settings of the Boot Loader bits affect the
BLB12
BLB12
5
5
BLB11
BLB11
4
4
51, or the interrupts must be disabled. Before
“Simple Assembly Code Example for a Boot
BLB02
BLB02
3
3
BLB01
BLB01
2
2
ck
bits). For future compati-
LB2
LB2
1
1
LB1
LB1
0
0
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