ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 191

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

Figure 20-6. Sampling of Data and Parity Bit
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling
20.8.3
9223B–AVR–09/11
(U2X = 0)
(U2X = 1)
(U2X = 0)
(U2X = 1)
Asynchronous Operational Range
Sample
Sample
Sample
Sample
RxD
RxD
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are empha-
sized on the figure by having the sample number inside boxes. The majority voting process is
done as follows: If two or all three samples have high levels, the received bit is registered to be
a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic
0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn
pin. The recovery process is then repeated until a complete frame is received. Including the
first stop bit. Note that the Receiver only uses the first stop bit of a frame.
Figure 20-7 on page 191
ning of the start bit of the next frame.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the
stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last
of the bits used for majority voting. For Normal Speed mode, the first low level sample can be
at point marked (A) in
to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or
too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar
(see
frames to the start bit.
1
1
1
1
Atmel ATmega48PA/88PA/168PA [Preliminary]
Table 20-2 on page
2
2
3
2
3
2
4
4
5
3
5
3
Figure
6
6
192) base frequency, the Receiver will not be able to synchronize the
shows the sampling of the stop bit and the earliest possible begin-
7
4
7
4
20-7. For Double Speed mode the first low level must be delayed
8
8
STOP 1
BIT n
9
5
9
5
10
10
(A)
0/1
11
6
6
0/1
12
(B)
0/1
0/1
13
7
14
15
8
16
(C)
1
1
191