ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 292

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

27.9
27.9.1
292
Register Description
Atmel ATmega48PA/88PA/168PA [Preliminary]
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to
control the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW
section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to
one after a Self-Programming operation is completed. Alternatively the RWWSB bit will auto-
matically be cleared if a page load operation is initiated.
• Bit 5 – Reserved
This bit is a reserved bit in the Atmel
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SELFPRGEN will be cleared).
Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be
re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If
the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort
and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The
data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be
cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four
clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the
SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the
Z-pointer) into the destination register. See
on page 285
Bit
0x37 (0x57)
Read/Write
Initial Value
for details.
SPMIE
R/W
7
0
RWWSB
R
6
0
R
5
–
0
®
RWWSRE
ATmega48PA/88PA/168PA and always read as zero.
R/W
4
0
“Reading the Fuse and Lock Bits from Software”
BLBSET
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
SELFPRGEN
R/W
0
0
9223B–AVR–09/11
SPMCSR