ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 13

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

7.5.1
7.6
9223B–AVR–09/11
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
the chip. No internal clock division is used.
Figure 7-4
Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS perMHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 7-4.
Figure 7-5
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 7-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an
shows the parallel instruction fetches and instruction executions enabled by the
Result Write Back
RAMEND
RAMEND
SP15
SP7
R/W
R/W
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
15
7
clk
clk
RAMEND
RAMEND
CPU
SP14
SP6
R/W
R/W
CPU
14
6
RAMEND
RAMEND
SP13
SP5
R/W
R/W
13
5
CPU
T1
T1
, directly generated from the selected clock source for
RAMEND
RAMEND
SP12
R/W
R/W
SP4
12
4
RAMEND
RAMEND
SP11
R/W
R/W
SP3
T2
11
T2
3
RAMEND
RAMEND
SP10
R/W
SP2
R/W
10
2
T3
T3
RAMEND
RAMEND
SP9
SP1
R/W
R/W
9
1
RAMEND
RAMEND
SP8
SP0
R/W
R/W
8
0
T4
T4
SPH
SPL
13