ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 81

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

8285D–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• XCK/AIN0/PCINT2 – Port E, Bit 2
XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is
output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper-
ates in synchronous mode.
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
• TXD/PCINT1 – Port E, Bit 1
TXD0, UART0 Transmit pin.
PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.
• RXD/PCINT0 – Port E, Bit 0
RXD, USART Receive pin. Receive Data (Data input pin for the USART). When the USART
Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the
USART forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.
Table 14-9
shown in
Table 14-9.
Note:
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. CKOUT is one if the CKOUT Fuse is programmed
Figure 14-5 on page
and
PE7/PCINT7
0
0
CKOUT
1
CKOUT
clk
–
PCINT7 • PCIE0
1
PCINT7 INPUT
–
Overriding Signals for Alternate Functions PE7:PE4
I/O
Table 14-10
(1)
(1)
relates the alternate functions of Port E to the overriding signals
PE6/DO/
PCINT6
0
0
0
0
USI_THREE-
WIRE
DO
–
PCINT6 • PCIE0
1
PCINT6 INPUT
–
74.
PE5/DI/SDA/
PCINT5
USI_TWO-WIRE
0
USI_TWO-WIRE
(SDA + PORTE5) •
DDE5
USI_TWO-WIRE •
DDE5
0
0
(PCINT5 • PCIE0) +
USISIE
1
DI/SDA INPUT
PCINT5 INPUT
–
PE4/USCK/SCL/
PCINT4
USI_TWO-WIRE
0
USI_TWO-WIRE
(USI_SCL_HOLD •
PORTE4) + DDE4
USI_TWO-WIRE • DDE4
0
USITC
(PCINT4 • PCIE0) +
USISIE
1
USCKL/SCL INPUT
PCINT4 INPUT
–
81