ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 198
ATmega325PA
Manufacturer Part Number
ATmega325PA
Description
Manufacturer
Atmel Corporation
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21. USI – Universal Serial Interface
21.1
21.2
8285D–AVR–06/11
Features
Overview
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
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The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
ment of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
Figure 21-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
USIDR
USICR
USISR
”Register Descriptions” on page
2
4-bit Counter
”Pin Configurations” on page
3
2
1
0
3
2
1
0
D Q
LE
[1]
Figure 22-1 on page
TIM0 COMP
0
1
206.
Two-wire Clock
Control Unit
2. CPU accessible I/O Registers,
CLOCK
HOLD
210. For the actual place-
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
198
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