ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 27
ATmega325PA
Manufacturer Part Number
ATmega325PA
Description
Manufacturer
Atmel Corporation
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8.6.4
8.6.5
8.6.6
8285D–AVR–06/11
EECR – EEPROM Control Register
GPIOR2 – General Purpose I/O Register 2
GPIOR1 – General Purpose I/O Register 1
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Reserved
These bits are reserved and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
Bit
0x1F (0x3F)
Read/Write
Initial Value
Bit
0x2B (0x4B)
Read/Write
Initial Value
Bit
0x2A (0x4A)
Read/Write
Initial Value
MSB
MSB
R/W
R/W
R
7
–
0
7
0
7
0
R/W
R/W
R
6
–
0
6
0
6
0
R/W
R/W
R
5
–
0
5
0
5
0
R/W
R/W
R
4
–
0
4
0
4
0
EERIE
R/W
R/W
R/W
3
0
3
0
3
0
EEMWE
R/W
R/W
R/W
2
0
2
0
2
0
EEWE
R/W
R/W
R/W
1
X
1
0
1
0
EERE
R/W
LSB
LSB
R/W
R/W
0
0
0
0
0
0
GPIOR2
GPIOR1
EECR
27
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